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Circello Joseph C, Riedel Klaus R: Data processor with built-in emulation circuit. Motorola, March 12, 1997: EP0762276-A1 (26 worldwide citation)

A data processor (3) executes a real time trace function which allows an external development system (7) to dynamically observe internal operations of data processor (3) without assuming a type or availability of an external bus and without significantly impacting the efficiency and speed of the dat ...


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Hohl William A, Circello Joseph C: Data processor with built-in emulation circuit. Motorola, March 12, 1997: EP0762280-A1 (17 worldwide citation)

A central processing unit (2) and a debug module (10) execute concurrent operations without requiring a data processor (3) to operate in a special debug mode. The use of a bus (25) to communicate data, address, and control information between a core (9) and debug module (10) allows debug module (10) ...


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Hinds Christopher N, Circello Joseph C, Hohl William A: Data processor with built-in emulation circuit. Motorola, March 12, 1997: EP0762278-A1 (12 worldwide citation)

A data processor (3) includes a plurality of hardware breakpoint registers (50) and a breakpoint circuit (100) to perform a breakpoint operation. The breakpoint operations may be based on a value of a program counter or a program counter mask, an operand address range, and a data value or data mask ...


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Circello Joseph C, Hohl William A: Data processor with built-in emulation circuit. Motorola, March 12, 1997: EP0762279-A1 (8 worldwide citation)

A data processor (3) executes a debug operation by minimally intruding on the real time operation of the data processor and without halting the data processor. The data processor implements a control register (40) which stores trigger response value for determining a function executed by the data pr ...


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Circello Joseph C: Data processor with built-in emulation circuit. Motorola, March 12, 1997: EP0762277-A1 (5 worldwide citation)

A data processor (3) executes a breakpoint operation before an exception processing routine for a reset operation is initiated. When an External Reset signal is asserted and subsequently negated, a window of time exists in which data processor (3) is quiescent before beginning an actual reset except ...


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Circello Joseph C, Wilhite John Edward, Trubisky Leonard G: Computer with multiple operating systems.. Honeywell Inf Systems, May 2, 1984: EP0107448-A2 (5 worldwide citation)

In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM unit is described for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM unit includes an input buffer unit 511 and a ...


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Circello Joseph C, Gay James G, Glover Clinton T, Traynor Kevin M: Programmable read/write access signal and method therefor. Motorola, October 8, 1997: EP0800139-A2 (1 worldwide citation)

A system bus controller (103) within a processor (101) includes programmable logic for different modes of chip enable signals on a per-address-space basis. This allows for a "glueless" interface (107) between the processor (101) and different types of external devices (111, 112, 113), such as memory ...


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Wilhite John E, Trubisky Leonard G, Shelly William A, Circello Joseph C, Guenthner Russell W: Central execution pipeline unit.. Honeywell Inf Systems, April 25, 1984: EP0106664-A2 (1 worldwide citation)

A central execution pipeline unit, for initiating the execution of instructions by a synchronous CPU, operates in 6 stages or cycles. Instructions are obtained in program order from an instruction fetch unit of the CPU. Stage 1: the address information of an instruction is used to form the carries a ...