1
Chiting Cheng, Chung Cheng Chou, Jonathan Tsung Yung Chang: SRAM read and write assist apparatus. Taiwan Semiconductor Manufacturing Company, Slater & Matsil L, January 14, 2014: US08630132 (57 worldwide citation)

A SRAM READ and WRITE assist apparatus comprises a bit line voltage tracking block, a READ assist timer, a READ assist unit, a WRITE assist unit a WRITE control unit. The bit line voltage tracking block detects a voltage on a tracking bit line coupled to a plurality of tracking memory cells. In resp ...


2
Chung Cheng Chou, Chien Hua Chuang: Refresh counter with dynamic tracking of process, voltage and temperature variation for semiconductor memory. Taiwan Semiconductor Manufacturing, Duane Morris, February 13, 2007: US07177220 (12 worldwide citation)

A method and system for DRAM refresh wherein the refresh rate is proportional to the current leakage of one or more sampling cells. The sampling cells selected are representative of the nominal leakage condition of the DRAM array and track the DRAM cell leakage rates, which are dependent upon manufa ...


3
Chien Hua Huang, Chung Cheng Chou: Circuit and method for self-refresh of DRAM cells through monitoring of cell leakage currents. Taiwan Semiconductor Manufacturing Company, Duane Morris, March 1, 2005: US06862239 (12 worldwide citation)

A circuit and a method for self refresh of DRAM cells are provided. The circuit comprises a bias generator and an oscillator. The bias generator comprises a first current generator, a second current generator and a converter. The first current generator generates a first leakage current of “0” state ...


4
Chung Cheng Chou: Reference voltage generator circuit having temperature and process variation compensation and method of manufacturing same. Taiwan Semiconductor Manufacturing Company, Baker & McKenzie, May 2, 2006: US07038530 (11 worldwide citation)

Disclosed herein is a reference voltage generator circuit for providing and regulating a reference voltage. In one embodiment, the generator circuit includes a first subcircuit configured to provide a bias current based on a supply voltage, where the bias current varies based on at least one perform ...


5
Yi Tzu Chen, Chia Wei Su, Ming Zhang Kuo, Chung Cheng Chou: Circuit and method for small swing memory signals. Taiwan Semiconductor Manufacturing, Slater & Matsil L, February 14, 2012: US08116149 (10 worldwide citation)

Circuits and methods for transmitting and receiving small swing differential voltage data to and from a memory are described. A plurality of memory cells is formed in arrays within a plurality of memory banks. Each memory bank is coupled to a pair of small swing differential voltage global bit lines ...


6
Ping Lin Yang, Hsin Hsin Ko, Chung Cheng Chou: Power-down circuit with self-biased compensation circuit. Taiwan Semiconductor Manufacturing Company, Slater & Matsil L, July 20, 2010: US07760009 (8 worldwide citation)

A circuit includes a first power supply node at a first power supply voltage; a gated-node; and a first control device coupled between the first power supply node and the gated-node. The first control device is configured to pass the first power supply voltage to the gated-node or to disconnect the ...


7
Ruei Chin Luo, Chung Cheng Chou, Ching Wei Wu: Multiple-time programmable electrical fuse utilizing MOS oxide breakdown. Taiwan Semiconductor Manufacturing Company, Baker & McKenzie, June 7, 2005: US06903436 (8 worldwide citation)

An improved a programmable electrical fuse device utilizing MOS oxide breakdown is described herein. The fuse device comprises a programmable MOS device having a first gate width, a reference MOS device having a second gate width that is substantially less than the first gate width, and a sense ampl ...


8
Chung Cheng Chou, Yue Der Chih: Operating resistive memory cell. Taiwan Semiconductor Manufacturing, November 24, 2015: US09196360 (7 worldwide citation)

A circuit that includes a current source and a current comparator is disclosed. The current source is connected to a resistive memory cell to generate a driving current thereto. The current comparator has a sensing node connected to the current source and the resistive memory cell to sense an inject ...


9
Chien Hua Huang, Chung Cheng Chou: Dynamic random access memory cell leakage current detector. Taiwan Semiconductor Manufacturing, Duane Morris, April 25, 2006: US07035131 (6 worldwide citation)

A circuit operable to measure leakage current in a Dynamic Random Access Memory (DRAM) is provided comprising a plurality of DRAM bit cell access transistors coupled to a common bit line, a common word line, and a common storage node, wherein said access transistors may be biased to simulate a corre ...


10
Jonathan Tsung Yung Chang, Cheng Hung Lee, Chung Cheng Chou, Hung Jen Liao, Bin Hau Lo: Method and apparatus for read assist to compensate for weak bit. Taiwan Semiconductor Manufacturing, Duane Morris, February 17, 2015: US08958232 (6 worldwide citation)

A memory assist apparatus includes a detection circuit and a compensation circuit. The detection circuit is configured to provide a detection signal indicating whether a bit line configured to provide read access to a data bit stored at a memory bit cell has a voltage below a predetermined threshold ...