1
Michael M Thackeray, Christopher S Johnson, Khalil Amine, Jaekook Kim: Lithium metal oxide electrodes for lithium cells and batteries. The University of Chicago, Emrich and Dithmar, January 13, 2004: US06677082 (100 worldwide citation)

A lithium metal oxide positive electrode for a non-aqueous lithium cell is disclosed. The cell is prepared in its initial discharged state and has a general formula xLiMO


2
Michael M Thackeray, Christopher S Johnson, Khalil Amine, Jaekook Kim: Lithium metal oxide electrodes for lithium cells and batteries. The University of Chicago, Emrich and Dithmar, January 20, 2004: US06680143 (85 worldwide citation)

A lithium metal oxide positive electrode for a non-aqueous lithium cell is disclosed. The cell is prepared in its initial discharged state and has a general formula xLiMO


3
Dirgha Khatri, Dail Robert Cox, Christopher S Johnson: Memory module with integrated bus termination. Micron Technology, Williams Morgan & Amerson P C, June 22, 2004: US06754129 (72 worldwide citation)

A memory module includes a memory device, a connector, a plurality of lines coupling the memory device and the connector, and termination circuitry coupled to at least a subset of the lines. A method for terminating a memory bus includes providing at least two expansion sockets coupled to the memory ...


4
Christopher S Johnson: Dynamically setting burst length of memory device by applying signal to at least one external pin during a read or write transaction. Micron Technology, Dickstein Shapiro, December 12, 2006: US07149824 (71 worldwide citation)

One or more external control pins and/or addressing pins on a memory device are used to set one or both of a burst length and burst type of the memory device.


5
Michael M Thackeray, Christopher S Johnson, Khalil Amine, Jaekook Kim: Lithium metal oxide electrodes for lithium cells and batteries. UChicago Argonne, Emrich & Dithmar, November 14, 2006: US07135252 (57 worldwide citation)

A lithium metal oxide positive electrode for a non-aqueous lithium cell is disclosed. The cell is prepared in its initial discharged state and has a general formula xLiMO2.(1-x)Li2M′O3 in which 0


6
Christopher S Johnson, Brian Johnson: Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency. Micron Technology, Dorsey & Whitney, August 23, 2005: US06934199 (36 worldwide citation)

A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, ...


7
Michael M Thackeray, Christopher S Johnson, Khalil Amine: Lithium metal oxide electrodes for lithium cells and batteries. UChicago Argonne, Olson & Cepuritis, Harry M Levy, Robert J Ross, December 23, 2008: US07468223 (31 worldwide citation)

A lithium metal oxide positive electrode for a non-aqueous lithium cell is disclosed. The cell is prepared in its initial discharged state and has a general formula xLiMO2.(1−x)Li2M′O3 in which 0


8

9
Michael M Thackeray, Christopher S Johnson, Naichao Li: Manganese oxide composite electrodes for lithium batteries. UChicago Argonne, Olson & Hierl, Harry M Levy, December 4, 2007: US07303840 (29 worldwide citation)

An activated electrode for a non-aqueous electrochemical cell is disclosed with a precursor of a lithium metal oxide with the formula xLi2MnO3.(1−x)LiMn2−yMyO4 for 0


10
Christopher S Johnson, Brian Johnson: Memory device and method having low-power, high write latency mode and high-power, low write latency mode and/or independently selectable write latency. Micron Technology, Dorsey & Whitney, April 11, 2006: US07027337 (28 worldwide citation)

A logic circuit operates write receivers in a dynamic random access memory device in either a low-power mode, high write latency mode or a high-power mode, low write latency mode. The logic circuit receives a first signal indicative of whether the high-power, low write latency mode has been enabled, ...