1
Kevin Kok Chan, Christopher Peter D Emic, Erin Catherine Jones, Paul Michael Solomon, Sandip Tiwari: Method for making bonded metal back-plane substrates. International Business Machines Corporation, McGinn & Gibb P C, May 2, 2000: US06057212 (138 worldwide citation)

A method of forming a semiconductor structure, includes steps of growing an oxide layer on a substrate to form a first wafer, separately forming a metal film on an oxidized substrate to form a second wafer, attaching the first and second wafers, performing a heat cycle for the first and second wafer ...


2
Nestor Alexander Bojarczuk Jr, Kevin Kok Chan, Christopher Peter D Emic, Evgeni Gousev, Supratik Guha, Paul C Jamison, Lars Ake Ragnarsson: Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier. International Business Machines Corporation, Wan Yee Cheung Esq, McGinn & Gibb PLLC, May 10, 2005: US06891231 (7 worldwide citation)

A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electro ...


3
Nestor Alexander Bojarczuk Jr, Kevin Kok Chan, Christopher Peter D Emic, Evgeni Gousev, Supratik Guha, Paul C Jamison, Lars Ake Ragnarsson: Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier. International Business Machines Corporation, Stephen C Kaufman Esq, McGinn IP Law Group PLLC, January 30, 2007: US07169674 (3 worldwide citation)

A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electro ...


4
Can Bayram, Christopher Peter D Emic, William J Gallagher, Effendi Leobandung, Devendra K Sadana: Group III nitride integration with CMOS technology. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, June 7, 2016: US09362281 (1 worldwide citation)

A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the ...


5
Can Bayram, Christopher Peter D Emic, William J Gallagher, Effendi Leobandung, Devendra K Sadana: Group III nitride integration with CMOS technology. INTERNATIONAL BUSINESS MACHINES CORPORATION, Scully Scott Murphy & Presser P C, Louis J Percello Esq, May 3, 2016: US09331076

A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the ...


6
Can Bayram, Christopher Peter D Emic, William J Gallagher, Effendi Leobandung, Devendra K Sadana: Group III nitride integration with CMOS technology. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, February 7, 2017: US09564526

A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the ...


7
Can Bayram, Christopher Peter D Emic, William J Gallagher, Effendi Leobandung, Devendra K Sadana: Group III nitride integration with CMOS technology. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, May 23, 2017: US09660069

A method of forming a structure that can be used to integrate Si-based devices, i.e., nFETs and pFETs, with Group III nitride-based devices is provided. The method includes providing a substrate containing an nFET device region, a pFET device region and a Group III nitride device region, wherein the ...


8
Alexander Bojarczuk, Kevin Kok Chan, Christopher Peter D Emic, Evgeni Gousev, Supratik Guha, Paul C Jamison, Lars Ake Ragnarsson: Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier. International business Machines Corporation, Mcginn & Gibb Pllc, December 19, 2002: US20020190302-A1

A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electro ...


9
Nestor Alexander Bojarczuk, Kevin Kok Chan, Christopher Peter D Emic, Evgeni Gousev, Supratik Guha, Paul C Jamison, Lars Ake Ragnarsson: Complementary metal oxide semiconductor (CMOS) gate stack with high dielectric constant gate dielectric and integrated diffusion barrier. International Business Machines Corporation, Mcginn & Gibb Pllc, July 21, 2005: US20050156257-A1

A diffusion barrier (and method for forming the diffusion barrier) for a field-effect transistor having a channel region and a gate electrode, includes an insulating material being disposed over the channel region. The insulating material includes nitrogen (N), and is disposed under the gate electro ...