1
Andrew J Walker, Mark G Johnson, N Johan Knall, Igor G Kouznetsov, Christopher J Petti: Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication. Matrix Semiconductor, Pamela J Squyres, May 3, 2005: US06888750 (302 worldwide citation)

A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on ...


2
Thomas H Lee, Vivek Subramanian, James M Cleeves, Andrew J Walker, Christopher J Petti, Igor G Kouznetzov, Mark G Johnson, Paul Michael Farmwald, Brad Herner: Monolithic three dimensional array of charge storage devices containing a planarized surface. Matrix Semiconductor, Foley & Lardner, April 19, 2005: US06881994 (250 worldwide citation)

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.


3
Christopher J Petti, S Brad Herner: Semiconductor device including junction diode contacting contact-antifuse unit comprising silicide. Matrix Semiconductor, Matrix Semiconductor, Pamela J Squyres, September 20, 2005: US06946719 (183 worldwide citation)

The invention provides for a vertically oriented junction diode having a contact-antifuse unit in contact with one of its electrodes. The contact-antifuse unit is formed either above or below the junction diode, and comprises a silicide with a dielectric antifuse layer formed on and in contact with ...


4
Michael A Vyvoda, S Brad Herner, Christopher J Petti, Andrew J Walker: Inverted staggered thin film transistor with salicided source/drain structures and method of making same. Matrix Semiconductor, Foley & Lardner, November 9, 2004: US06815781 (112 worldwide citation)

A semiconductor device, such as an inverted staggered thin film transistor, includes a gate electrode, a gate insulating layer located above the gate electrode, an active layer located above the gate insulating layer and an insulating fill layer located above the active layer. A first opening and a ...


5
Roy E Scheuerlein, Christopher J Petti: High density contact to relaxed geometry layers. Sandisk 3D, Dugan & Dugan PC, January 6, 2009: US07474000 (100 worldwide citation)

The present invention provides for a via and staggered routing level structure. Vertically overlapping vias connect to two or more routing levels formed at different heights. The routing levels are either both formed above or both formed below the vias, and all are formed above a semiconductor subst ...


6
Thomas H Lee, Andrew J Walker, Christopher J Petti, Igor G Kouznetzov: Rail stack array of charge storage devices and method of making same. Matrix Semiconductor, Foley & Lardner, January 31, 2006: US06992349 (71 worldwide citation)

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.


7
S Brad Herner, Christopher J Petti: Selective germanium deposition for pillar devices. Sandisk 3D, Foley & Lardner, June 29, 2010: US07745312 (56 worldwide citation)

A method of making a pillar device includes providing an insulating layer having an opening, and selectively depositing germanium or germanium rich silicon germanium semiconductor material into the opening to form the pillar device.


8
Roy E Scheuerlein, Christopher J Petti: High bandwidth one time field-programmable memory. SanDisk 3D, Vierra Magen Marcus & DeNiro, March 3, 2009: US07499355 (46 worldwide citation)

A one-time field programmable (OTP) memory cell with related manufacturing and programming techniques is disclosed. An OTP memory cell in accordance with one embodiment includes at least one resistance change element in series with a steering element. The memory cell is field programmed using a reve ...


9
Christopher J Petti, Roy E Scheuerlein, Tanmay Kumar, Abhijit Bandyopadhyay: Transistor layout configuration for tight-pitched memory array lines. Matrix Semiconductor, Zagorin O Brien Graham, May 30, 2006: US07054219 (41 worldwide citation)

A multi-headed word line driver circuit incorporates bent-gate transistors to reduce the pitch otherwise achievable for interfacing to tightly-pitched array lines. In certain exemplary embodiments, a three-dimensional memory array includes multiple memory blocks and array lines traversing horizontal ...


10
Luca G Fasoli, Christopher J Petti, Roy E Scheuerlein: Method for using a passive element memory array incorporating reversible polarity word line and bit line decoders. SanDisk 3D, Zagorin O Brien Graham, December 9, 2008: US07463546 (34 worldwide citation)

Circuits and methods are described for decoding exemplary memory arrays of programmable and, in some embodiments, re-writable passive element memory cells, which are particularly useful for extremely dense three-dimensional memory arrays having more than one memory plane. In addition, circuits and m ...