1
Laurence H Cooke, Christopher E Phillips, Dale Wong: Integrated processor and programmable data path chip for reconfigurable computing. Burns Doane Swecker & Mathis, October 19, 1999: US05970254 (250 worldwide citation)

A reconfigurable processor chip has a mixture of reconfigurable arithmetic cells and logic cells for higher effective utilization than a standard FPGA. The reconfigurable processor includes a standard microprocessor such as an embedded RISC processor. Many different types of interfaces are used to i ...


2
Dale Wong, Christopher E Phillips, Laurence H Cooke: Integrated processor and programmable data path chip for reconfigurable computing. Chameleon Systems, Burns Doane Swecker & Mathis, August 28, 2001: US06282627 (235 worldwide citation)

The present invention, generally speaking, provides a reconfigurable computing solution that offers the flexibility of software development and the performance of dedicated hardware solutions. A reconfigurable processor chip includes a standard processor, blocks of reconfigurable logic (


3
Laurence H Cooke, Christopher E Phillips, Dale Wong: Method for compiling high level programming languages into an integrated processor with reconfigurable logic. Burns Doane Swecker & Mathis, October 12, 1999: US05966534 (198 worldwide citation)

A method is presented for automatically compiling a high level computer program down into an application specific integrated circuit coupled with a generic microprocessor. The original source code is written in a standard programming language such as ANSI C. Source code analysis is performed by our ...


4
Christopher E Phillips, Dale Wong, Karl W Pfalzer: Behavioral silicon construct architecture and mapping. Chameleon Systems, Burns Doane Swecker & Mathis, October 2, 2001: US06298472 (125 worldwide citation)

A system and method of logic synthesis uses a behavioral synthesis tool to convert a behavioral language description (e.g., behavioral description code, an intuitive algorithm, or programming language description) of an ASIC into a partitioned RTL language description including RTL sub-descriptions ...


5
Shaila Hanrahan, Christopher E Phillips: Control fabric unit including associated configuration memory and PSOP state machine adapted to provide configuration address to reconfigurable functional unit. Chameleon Systems, Burns Doane Swecker & Mathis, February 19, 2002: US06349346 (100 worldwide citation)

A reconfigurable system is arranged to have separate control and the data paths. The control path is set up using control fabric units which use an associated state machine to produce an address to a functional unit memory. The functional unit memory then produces the configuration data for the func ...


6
Christopher E Phillips, Dale Wong, Laurence H Cooke: Reconfigurable logic for table lookup. Chameleon Systems, Burns Doane Swecker & Mathis, May 14, 2002: US06389579 (99 worldwide citation)

An integrated circuit which contains a processor, and configurable logic with configuration memory such that the configurable logic can emulate a large memory array when the contents of the array are very sparse. This structure allows for fast access and a continuous updating capability while remain ...


7
Shaila Hanrahan, Christopher E Phillips: Configuration state memory for functional blocks on a reconfigurable chip. Chameleon Systems, Burns Doane Swecker & Mathis, September 11, 2001: US06288566 (95 worldwide citation)

A configuration state memory is associated with a configurable functional block on a reconfigurable chip. The configuration state memory stores more than one configuration for the functional block. This allows the functional block to switch configurations without requiring the configuration data to ...


8
Shaila Hanrahan, Christopher E Phillips: Reconfigurable program sum of products generator. Chameleon Systems, Burns Doane Swecker & Mathis, October 30, 2001: US06311200 (91 worldwide citation)

A reconfigurable programmable sum of products generator allows for multiple configurations to be associated with a programmable sum of products generator. These configurations can be modified by changing the configurations in an associated configuration memory for the programmable sum of products ge ...


9
Laurence H Cooke, Christopher E Phillips, William J Allen: Preprogramming testing in a field programmable gate array. Crosspoint Solutions, Townsend and Townsend Khourie and Crew, September 13, 1994: US05347519 (90 worldwide citation)

A field programmable gate array integrated circuit which has numerous features for testing prior to programming the antifuses in the integrated circuit is provided. The circuits used to program the antifuses are also used for much of the preprogramming testing. The functionality of continuous series ...


10
Laurence H Cooke, Christopher E Phillips, Dale Wong: Method for compiling high level programming languages into embedded microprocessor with multiple reconfigurable logic. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 16, 2004: US06708325 (87 worldwide citation)

A computer implemented method for automatically compiling a computer program written in a high level programming language into an intermediate data structure. The data structure is analyzed to identify critical blocks of logic, which can be implemented as an application specific integrated circuit ( ...