1
Pradeep Kumar Dubey, Charles Marshall Barton, Chiao Mei Chuang, Linh Hue Lam, John Kevin O Brien, Kathryn Mary O Brien: Executing speculative parallel instructions threads with forking and inter-thread communication. International Business Machines Corporation, Louis J Percello, September 22, 1998: US05812811 (141 worldwide citation)

A central processing unit (CPU) in a computer that permits speculative parallel execution of more than one instruction thread. The CPU uses Fork-Suspend instructions that are added to the instruction set of the CPU, and are inserted in a program prior to run-time to delineate potential future thread ...


2
Chiao Mei Chuang: Performance enhancement scheme for a RISC type VLSI processor using dual execution units for parallel instruction processing. International Business Machines, C Lamont Whitham, Michael E Whitham, August 23, 1988: US04766566 (119 worldwide citation)

Performance of a VLSI processor of the reduced instruction set computer (RISC) type is enhanced by executing two instructions simultaneously in the two execution units of the processor. There is very little increase in the cost of hardware. Three embodiments are presented with different cost and per ...


3
Chiao Mei Chuang, Richard E Matick, Fred T Tong: Functional cache memory chip architecture for improved cache access. International Business Machines Corporation, Roy R Schlemmer Jr, February 27, 1990: US04905188 (58 worldwide citation)

An on-chip VLSI cache architecture including a single-port, last-select, cache array organized as an n-way set-associative cache (having n congruence classes) including a plurality of functionally integrated units on-chip in addition to the cache array and including a normal read/write CPU access fu ...


4
Chiao Mei Chuang: Apparatus for concurrent multiple instruction decode in variable length instruction set computer. International Business Machines Corporation, Marc D Schechter, Robert P Tassinari Jr, December 6, 1994: US05371864 (51 worldwide citation)

A data processing apparatus for simultaneously reading out groups of two or more contiguous, variable length instructions from memory, and for decoding the group of variable length instructions in parallel. The data processing apparatus has a memory containing at least first, second, and third conti ...


5
Chiao Mei Chuang, Hung Qui Le: Method and system for managing registers in a data processing system supports out-of-order and speculative instruction execution. International Business Machines Corporation, Anthony V S England, Bracewell & Patterson L, March 12, 2002: US06356918 (48 worldwide citation)

A method and a system in a data processing system for managing registers in a register array wherein the data processing system has M architected registers and the register array has greater than M registers. A first physical register address is selected from a group of available physical register a ...


6
Quinn A Jacobson, Chiao Mei Chuang: Backing Register File for processors. Sun Microsystems, Martine Penilla & Gencarella, April 17, 2007: US07206925 (21 worldwide citation)

A processor is defined by a new architectural feature called a Backing Register File, where a Backing Register File is a set of randomly accessible registers capable of holding values, and further are directly connected to the processor's register files. The processor's register files are in turn co ...


7
Chiao Mei Chuang, Kemal Ebciogulu: General purpose memory access scheme using register-indirect mode. International Business Machines Corporation, Robert P Tassinari Jr, November 22, 1994: US05367648 (4 worldwide citation)

A memory access scheme achieved using a memory address register and a register-indirect memory accessing mode eliminates write back collisions, long cycle time, and enhances system performance. During memory address generation operations, an arithmetic-logic unit (ALU) generates memory addresses fro ...


8
Quinn A Jacobson, Chiao Mei Chuang: Explicitly clustered register file and execution unit architecture. Sun Microsystems, Martine & Penilla, June 29, 2004: US06757807 (4 worldwide citation)

A processor comprising a new architectural feature called a Register Domain, where a Register Domain has a register file, at least one execution unit, and coupling circuitry between the two. A processor will typically have a plurality of Register Domains, and Register Domains may have different type ...


9
Kin Shing Chan, Chiao Mei Chuang, Sang Hoo Dhong, Alessandro Marchioro: Fast multiple operands adder/subtracter based on shifting. International Business Machines Corporation, Kevin M Jordan, July 7, 1998: US05777918 (2 worldwide citation)

A fast adder/subtracter using a decoder and shifting function instead of conventional full-adders is disclosed. The circuit is optimized for the addition of multiple operands up to 4-5 binary bits in magnitude. Using this method a subtraction operation can be performed at no added cost with respect ...


10
Kin Shing Chan, Chiao Mei Chuang, Alessandro Marchioro: Method and apparatus for reconstructing the address of the next instruction to be completed in a pipelined processor. International Business Machines Corporation, Jay P Sbrollini, February 6, 2001: US06185674 (1 worldwide citation)

A computer processing unit is provided that includes an apparatus for generating an address of the next instruction to be completed. The apparatus includes a first table for storing a plurality of entries each corresponding to a dispatched instruction, each entry comprising an identifier that identi ...