1
Jeff J Xu, Chia Ta Hsieh, Chun Pei Wu, Chun Hung Lee: Storage nitride encapsulation for non-planar sonos NAND flash charge retention. Taiwan Semiconductor Manufacturing Company, Haynes and Boone, March 22, 2011: US07910453 (141 worldwide citation)

The present disclosure provides a method of manufacturing a microelectronic device. The method includes forming recessed shallow trench isolation (STI) features in a semiconductor substrate, defining a semiconductor region between adjacent two of the recessed STI features; forming a tunnel dielectri ...


2
Chia Ta Hsieh: Split-gate flash with source/drain multi-sharing. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, November 16, 2004: US06818512 (36 worldwide citation)

A multi-bit split-gate (MSG) flash cell with multi-shared source/drain and making of the same are disclosed. The MSG is formed with N+1 stacked gates comprising floating gates and control gates, separated by N select gates, all sharing the same source/drain between a pair of bit lines. With the ...


3
Hung Cheng Sung, Di Son Kuo, Chia Ta Hsieh, Yai Fen Lin: Poly tip formation and self-align source process for split-gate flash cell. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, September 12, 2000: US06117733 (32 worldwide citation)

A novel method of forming a first polysilicon gate tip (poly tip) for enhanced F-N tunneling in split-gate flash memory cells is disclosed. The poly tip is further enhanced by forming a notch in two different ways in a nitride layer overlying the first polysilicon layer. In one embodiment, the notch ...


4
Chia Ta Hsieh, Hung Cheng Sung, Yai Fen Lin, Jack Yeh, Di Son Kuo: Method to fabricate split-gate with self-aligned source and self-aligned floating gate to control gate. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Sevgin Oktay, May 8, 2001: US06228695 (32 worldwide citation)

A split-gate flash memory cell having self-aligned source and floating gate self-aligned to control gate is disclosed as well as a method of forming the same. This is accomplished by depositing over a gate oxide layer on a silicon substrate a poly-1 layer to form a vertical control gate followed by ...


5
Chia Ta Hsieh, Yai Fen Lin, Di Son Kuo, Hung Cheng Sung, Jack Yeh: Method to increase coupling ratio of source to floating gate in split-gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, December 12, 2000: US06159801 (29 worldwide citation)

A split-gate flash memory cell having a three-dimensional source capable of three-dimensional coupling with the floating gate of the cell, as well as a method of forming the same are provided. This is accomplished by first forming an isolation trench, lining it with a conformal oxide, then filling w ...


6
Wen Ting Chu, Di Son Kuo, Jack Yeh, Chia Ta Hsieh, Chuan Li Chang: Method of forming a floating gate self-aligned to STI on EEPROM. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Sergin O Ktay, June 11, 2002: US06403494 (27 worldwide citation)

A method is disclosed for forming a split-gate flash memory cell where the floating gate of the cell is self-aligned to a shallow trench isolation (STI), which in turn makes it self-aligned to source and to word line. This will advantageously affect a shrinkage in the size of the memory cell. In a f ...


7
Chrong Jung Lin, Sheng Wei Tsao, Di Son Kuo, Jack Yeh, Wen Ting Chu, Chung Li Chang, Chia Ta Hsieh: Vertical split gate field effect transistor (FET) device. Taiwan Semiconductor Manufacturing, Tung & Associates, October 15, 2002: US06465836 (27 worldwide citation)

Within both a split gate field effect transistor (FET) device and a method for fabricating the split gate field effect transistor (FET) device there is formed within a semiconductor substrate a trench within whose sidewall is fully contained a channel region within the split gate field effect transi ...


8
Chia Ta Hsieh, Yai Fen Lin, Hung Cheng Sung, Chuang Ke Yeh, Di Son Kuo: Method of fabricating step poly to improve program speed in split gate flash. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, March 9, 1999: US05879992 (23 worldwide citation)

A method is provided for forming a split-gate flash memory cell having a step poly supporting an interpoly oxide of varying thickness for the purposes of improving the over-all performance of the cell. Polyoxide is formed over portions of a first polysilicon layer which in turn is partially etched t ...


9
Chia Ta Hsieh: Flash EEPROM with function bit by bit erasing. Taiwan Semiconductor Manufacturing, Thomas Kayden Horstemeyer & Risley, August 23, 2005: US06933555 (23 worldwide citation)

A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a po ...


10
Chia Ta Hsieh: Flash EEPROM with function bit by bit erasing. Taiwan Semiconductor Manufacturing Company, George O Saile, Stephen B Ackerman, Douglas R Schnabel, November 11, 2003: US06645813 (23 worldwide citation)

A multi-bit split-gate (MSG) flash cell with multi-shared source/drain, a method of making and a method of programming the same are disclosed. Furthermore, a method of bit-by-bit erasing, in addition to page erasing, of a plurality of cells of two or more is disclosed through the application of a po ...