1
William Panepinto Jr, Chester M Nibby Jr: Memory present apparatus. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, Ronald T Reiling, December 1, 1981: US04303993 (96 worldwide citation)

A memory subsystem includes at least one up to a number of memory module boards identical in layout and construction. The board includes a number of memory chips which are positioned in a number of physical row locations together providing a predetermined number of addressable contiguous memory loca ...


2
Raymond D Bowden III, Chester M Nibby Jr: High speed burst read address generation with high speed transfer. Bull HN Information Systems, Faith F Driscoll, John S Solakian, September 6, 1994: US05345573 (81 worldwide citation)

A memory system coupled to a local bus of a microprocessor includes at least a pair of dynamic random access memories (DRAMs) and includes circuits for storing the first address of an address sequence at the beginning of each burst operation and uses predetermined bits to generate any one of a set o ...


3
Robert B Johnson, Chester M Nibby Jr, Dana Moore: Sequential chip select decode apparatus and method. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, April 6, 1982: US04323965 (73 worldwide citation)

A memory subsystem which couples to a multiword bus for processing memory requests received therefrom includes at least a pair of independently addressable dynamic memory module units. Each memory unit includes a number of rows of random access memory (RAM) chips. The subsystem receives as part of e ...


4
James F Bertone, Bruno DiPlacido Jr, Thomas F Joyce, Martin Massucci, Lance J McNally, Thomas L Murray Jr, Chester M Nibby Jr, Michelle A Pence, Marc Sanfacon, Jian Kuo Shen, Jeffrey S Somers, G Lewis Steiner: Symmetric multiprocessing system with unified environment and distributed system functions. Zenith Data Systems Corporation, Fitch Even Tabin & Flannery, May 14, 1996: US05517648 (72 worldwide citation)

A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assum ...


5
Chester M Nibby Jr, Reeni Goldin, Timothy A Andrews: Remap method and apparatus for a memory system which uses partially good memory devices. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, July 2, 1985: US04527251 (70 worldwide citation)

A remapping method and apparatus is employed by a memory controller system which includes a microprocessing section which couples to a memory section. The memory section includes a partially good bulk random access memory constructed from a plurality of bit wide chips containing a predefined small n ...


6
Robert B Johnson, Chester M Nibby Jr, Edward R Salas: Identification apparatus for use in a controller to facilitate the diagnosis of faults. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, August 28, 1984: US04468731 (69 worldwide citation)

A data processing system includes a main memory system which couples in common with a central processing unit to a bus for transfer of data between the central processing unit and memory system. The memory system includes a plurality of memory controllers, each of which controls the operation of a n ...


7
Robert B Johnson, Chester M Nibby Jr: Memory controller with queue control apparatus. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, December 28, 1982: US04366538 (62 worldwide citation)

A memory controller couples to a bus and controls a number of memory module units or memory modules. The controller includes a number of queue circuits for processing a variety of different types of memory requests received from a number of command generating units coupled to the bus requiring the c ...


8
Robert B Johnson, Chester M Nibby Jr, Edward R Salas: Memory system with automatic memory configuration. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, March 26, 1985: US04507730 (57 worldwide citation)

A memory system includes a plurality of memory controllers which connect to a common bus. Each memory controller includes reconfiguration apparatus which enables the controller when faulty to be switched off line and another controller to be substituted in its place so as to maintain system memory c ...


9
James F Bertone, Bruno DiPlacido Jr, Thomas F Joyce, Martin Massucci, Lance J McNally, Thomas L Murray Jr, Chester M Nibby Jr, Michelle A Pence, Marc Sanfacon, Jian Kuo Shen, Jeffrey S Somers, G Lewis Steiner, William S Wu, Norman J Rasmussen, Suresh K Marisetty, Puthiya K Nizar: Adaptively generating timing signals for access to various memory devices based on stored profiles. Packard Bell NEC, Fitch Even Tabin & Flannery, September 15, 1998: US05809340 (50 worldwide citation)

Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a m ...


10
Edward R Salas, Edwin P Fisher, Robert B Johnson, Chester M Nibby Jr, Daniel A Boudreau: Memory identification apparatus and method. Honeywell Information Systems, Faith F Driscoll, Nicholas Prasinos, October 1, 1985: US04545010 (45 worldwide citation)

A memory system includes at least one or more memory module boards identical in construction and a single computer board containing the control circuits for controlling memory operations. Each board plugs into the main board and includes a memory section having a number of rows of memory chips and a ...