1
Anirban Basu, Cheng Wei Cheng, Amlan Majumdar, Ryan M Martin, Uzma Rana, Devendra K Sadana, Kuen Ting Shiu, Yanning Sun: III-V finFETs on silicon substrate. International Business Machines Corporation, Tutunjian & Bitetto P C, Louis J Percello, January 20, 2015: US08937299 (12 worldwide citation)

A method for forming fin field effect transistors includes forming a dielectric layer on a silicon substrate, forming high aspect ratio trenches in the dielectric layer down to the substrate, the high aspect ratio including a height to width ratio of greater than about 1:1 and epitaxially growing a ...


2
Anirban Basu, Cheng Wei Cheng, Wilfried E Haensch, Amlan Majumdar, Kuen Ting Shiu: Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts. International Business Machines Corporation, Maeve McCarthy, March 15, 2016: US09287362 (6 worldwide citation)

An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a ...


3
Tze Chiang Chen, Cheng Wei Cheng, Devendra K Sadana, Kuen Ting Shiu: Co-integration of elemental semiconductor devices and compound semiconductor devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, September 23, 2014: US08841177 (4 worldwide citation)

First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first ...


4
Tze Chiang Chen, Cheng Wei Cheng, Devendra K Sadana, Kuen Ting Shiu: Co-integration of elemental semiconductor devices and compound semiconductor devices. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, March 10, 2015: US08975635 (4 worldwide citation)

First and second template epitaxial semiconductor material portions including different semiconductor materials are formed within a dielectric template material layer on a single crystalline substrate. Heteroepitaxy is performed to form first and second epitaxial semiconductor portions on the first ...


5
Can Bayram, Cheng Wei Cheng, Devendra K Sadana, Kuen Ting Shiu: Dual phase gallium nitride material formation on (100) silicon. INTERNATIONAL BUSINESS MACHINES CORPORATION, Scully Scott Murphy & Presser P C, Louis J Percello Esq, June 2, 2015: US09048173 (3 worldwide citation)

A method for selective formation of a dual phase gallium nitride material on a (100) silicon substrate. The method includes forming a blanket layer of dielectric material on a surface of a (100) silicon substrate. The blanket layer of dielectric material is then patterned forming a plurality of patt ...


6
Cheng Wei Cheng, Ning Li, Kuen Ting Shiu: High throughput epitaxial liftoff for releasing multiple semiconductor device layers from a single base substrate. International Business Machines Corporation, Scully Scott Murphy & Presser P C, Louis J Percello Esq, July 23, 2013: US08492187 (3 worldwide citation)

A multilayered stack including alternating layers of sacrificial material layers and semiconductor material layers is formed on a base substrate. The thickness of each sacrificial material layer of the stack increases upwards from the sacrificial material layer that is formed nearest to the base sub ...


7
Cheng Wei Cheng, David L Rath, Devendra K Sadana, Kuen Ting Shiu, Brent A Wacaser: Enhanced defect reduction for heteroepitaxy by seed shape engineering. International Business Machines Corporation, Tutinjian & Bitetto P C, Louis J Percello, February 7, 2017: US09564494 (2 worldwide citation)

A heteroepitaxially grown structure includes a substrate and a mask including a high aspect ratio trench formed on the substrate. A cavity is formed in the substrate having a shape with one or more surfaces and including a resistive neck region at an opening to the trench. A heteroepitaxially grown ...


8
Cheng Wei Cheng, Pranita Kerber, Young Hee Kim, Effendi Leobandung, Yanning Sun: Reduced current leakage semiconductor device. International Business Machines Corporation, Steven F McDaniel, July 19, 2016: US09397161 (2 worldwide citation)

A method for fabricating a semiconductor device may include receiving a gated substrate comprising a substrate with a channel layer and a gate structure formed thereon, over-etching the channel layer to expose an extension region below the gate structure, epitaxially growing a halo layer on the expo ...


9
Cheng Wei Cheng, Shu Jen Han, Kuen Ting Shiu: Self-aligned III-V field effect transistor (FET), integrated circuit (IC) chip with self-aligned III-V FETS and method of manufacture. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, June 18, 2013: US08466493 (2 worldwide citation)

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations are defined on a layered semiconductor wafer. The layered semiconductor wafer preferably includes a III-V semiconductor surface layer, e.g., Gallium Arsenide (GaA ...


10
Anirban Basu, Cheng Wei Cheng, Wilfried E Haensch, Amlan Majumdar, Kuen Ting Shiu: Vertical field effect transistors with controlled overlap between gate electrode and source/drain contacts. International Business Machines Corporation, Maeve Carpenter, July 19, 2016: US09397226 (2 worldwide citation)

An approach to forming a semiconductor structure for a vertical field effect transistor with a controlled gate overlap. The approach includes forming on a semiconductor substrate, a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, a fourth semiconductor layer, a ...