1
Gigy Baror, Brian W Case, Rod G Fleck, Philip M Freidin, Smeeta Gupta, William M Johnson, Cheng Gang Kong, Ole H Moller, Timothy A Olson, David I Sorensen: Streamlined instruction processor. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, May 15, 1990: US04926323 (137 worldwide citation)

A streamlined instruction processor processes data in response to a program composed of prespecified instructions in pipeline cycles. The processor comprises an instruction fetch unit, including an instruction interface adapted for connection to an instruction memory and for fetching instructions fr ...


2
Brian W Case, Rod G Fleck, Cheng Gang Kong, Ole Moller: System for processing single-cycle branch instruction in a pipeline having relative, absolute, indirect and trap addresses. Advanced Micro Devices, Kenneth B Salomon, J Vincent Tortolano, October 11, 1988: US04777587 (91 worldwide citation)

An instruction processor suitable for use in a reduced instruction-set computer employs an instruction pipeline which performs conditional branching in a single processor cycle. The processor treats a branch condition as a normal instruction operand rather than a special case within a separate condi ...


3
William M Johnson, Rod G Fleck, Cheng Gang Kong, Ole Moller: Mechanism for performing data references to storage in parallel with instruction execution on a reduced instruction-set processor. Advanced Micro Devices, Patrick T King, Kenneth B Salomon, J Vincent Tortolano, March 29, 1988: US04734852 (53 worldwide citation)

A simple architecture to implement a mechanism for performing data references to storage in parallel with instruction execution. The architecture is particularly suited to reduced instruction-set computers (RISCs) and employs a channel address register to store the main memory load or store address, ...


4
Brian W Case, Rod G Fleck, William M Johnson, Cheng Gang Kong, Ole Moller: General-purpose register file optimized for intraprocedural register allocation, procedure calls, and multitasking performance. Advanced Micro Devices, Kenneth B Salomon, J Vincent Tortolano, October 11, 1988: US04777588 (29 worldwide citation)

A high speed register file for use by an instruction processor suitable for reduced instruction-set computers (RISCs) is disclosed which is preferably used with an efficient register allocation method. The register file facilitates the passing of parameters between procedures by dynamically providin ...


5
Victor Suen, William Lau, Hong Him Lim, Cheng Gang Kong: Apparatus and methods for improved input/output cells. LSI Corporation, Duft Bornsen & Fishman, July 3, 2007: US07239170 (23 worldwide citation)

Apparatus and methods are provided for improving data exchanges between electronic devices, such as memory controllers and RLDRAMs. An I/O cell includes a signal pad for transferring a first signal to an electronic device coupled thereto and for receiving a second signal from the electronic device. ...


6
Thomas Hughes, Cheng Gang Kong: System and method for providing swap path voltage and temperature compensation. LSI Logic Corporation, Suiter Swantz pc llo, August 4, 2009: US07571396 (16 worldwide citation)

The present invention is a method for data path voltage and temperature compensation. The method includes configuring an offline data path to match an online data path. The method further includes compensating the offline data path for voltage and temperature variation. The method further includes s ...


7
Derrick Sai Tang Butt, Cheng Gang Kong, Terence J Magee: Configurable high-speed memory interface subsystem. LSI Corporation, Christopher P Maiorana PC, October 14, 2008: US07437500 (15 worldwide citation)

A core including a write logic IP block, a read logic IP block, a master delay IP block and an address and control IP block. The write logic IP block may be configured to communicate data from a memory controller to a double data rate (DDR) synchronous dynamic random access memory (SDRAM). The read ...


8
Cheng Gang Kong, Victor Suen: Wide-range programmable delay line. LSI Logic Corporation, Christopher P Maiorana, October 10, 2006: US07119596 (12 worldwide citation)

An apparatus comprising an input section, a first delay circuit and a second delay circuit. The input section may be configured to present a first intermediate signal by selecting either (i) an input clock signal or (ii) a feedback of an output signal. The first delay circuit may be configured to ge ...


9
Terence Magee, Thomas Hughes, Cheng Gang Kong: System and method for compensating for PVT variation effects on the delay line of a clock signal. LSI Logic Corporation, Suiter Swantz PC LLO, November 18, 2008: US07454303 (10 worldwide citation)

The present invention is directed to a method for compensating for process, voltage, and temperature variation without complex online/offline swapping of data paths requiring a dedicated FIFO(First-in First-out) buffer design. Delay cells are trained for each clock path (namely a Functional delay) a ...


10
Cheng Gang Kong, Thomas Hughes: Apparatus and systems for VT invariant DDR3 SDRAM write leveling. LSI Corporation, Duft Bornsen & Fishman, November 23, 2010: US07839716 (9 worldwide citation)

Apparatus and systems for improved PVT invariant fast rank switching in a DDR3 memory subsystem. A clock skew control circuit is provided between a memory controller and a DDR3 SDRAM memory subsystem to adjust skew between the DDR3 clock signal and data related signals (e.g., DQ and/or DQS). A initi ...