1
Edmond J Boufarah, Gregory F Grohoski, Chien Chyun Lee, Charles R Moore: System for reducing delay in instruction execution by executing branch instructions in separate processor while dispatching subsequent instructions to primary processor. International Business Machines Corporation, Thomas E Tyson, June 30, 1992: US05127091 (84 worldwide citation)

A data processing system including a circuit for storing a sequence of instructions, a circuit for determining if the instruction sequence includes a branch instruction, a circuit for storing a sequence of branch target instructions in response to the determination of the existence of a branch instr ...


2
Charles R Moore, John S Muhich, Robert J Reese: System and method for transferring information between multiple buses. International Business Machines Corporation, Michael A Davis Jr, March 11, 1997: US05611058 (81 worldwide citation)

A method and system are provided for transferring information between multiple buses. Information is transferred through a first bus between multiple first bus devices. Information is transferred through a second bus between multiple second bus devices. Information is transferred through logic betwe ...


3
Samuel T Costanza, Peter G Franklin, Frank L Gebhardt, Jack D Israel, Charles R Moore, Charles E Wheatley III: Communication system. Rockwell International Corporation, L Lee Humphries, H Fredrick Hamann, Rolf M Pitts, January 3, 1978: US04066964 (76 worldwide citation)

This invention relates to a communication system wherein a plurality of stations can communicate with each other, without going through a central switchboard; and more particularly to such a communication system that is as private as possible -- the commmunication system having, in addition, the cap ...


4
Charles R Moore, John S Muhich: Method and system for maintaining translation lookaside buffer coherency in a multiprocessor data processing system. International Business Machines Corporation, Michael A Davis, Andrew J Dillon, July 25, 1995: US05437017 (57 worldwide citation)

Translation lookaside buffers (TLB) are often utilized in the data processing system to efficiently translate an effective or virtual address to a real address within system memory. In systems which include multiple processors which may all access system memory, each processor may include a translat ...


5
Tan V Chu, Charles R Moore, John S Muhich, Terence M Potter: Method and system for distributed instruction address translation in a multiscalar data processing system. International Business Machines Corporation, Michael A Davis, Andrew J Dillon, August 15, 1995: US05442766 (28 worldwide citation)

A method and system for distributed instruction address translation in a multiscalar data processing system having multiple processor units for executing multiple tasks, instructions and data stored within memory at real addresses therein and a fetcher unit for fetching and dispatching instructions ...


6
Michael C Becker, Charles R Moore, John S Muhich, Robert J Reese: Data processor with speculative data transfer and address-free retry. Motorola, Lee E Chastain, March 19, 1996: US05500950 (22 worldwide citation)

A data processor with speculative data transfer has address circuitry (40) and data circuitry (42, 44). The address circuitry generates a memory address associated with a data block and with a tag. The tag is representative of the validity of the data block. The data circuitry receives the data bloc ...


7
Charles R Moore: Emergency lamp. Blanchard Flynn Thiel Boutell & Tanis, February 21, 1978: US04075470 (16 worldwide citation)

A portable electric lamp generally designed to connect to the electrical supply system in an automobile. The portable electric lamp as a base and a pair of feet pivotally secured to the base at spaced locations thereon and about parallel axes. A U-shaped bracket having a pair of upstanding and paral ...


8
Chien Chyun Lee, Charles R Moore: Dynamic buffer control. International Business Machines Corporation, Thomas E Tyson, April 10, 1990: US04916658 (14 worldwide citation)

A buffer for storing data words consisting of several storage locations together with circuitry providing a first indicator that designates the next storage location to be stored into, a second indicator designating the next storage location to be retrieved from, and circuitry that provides the numb ...


9
Charles R Moore: Processor and method of testing a processor for hardware faults utilizing a pipeline interlocking test instruction. August 22, 2006: US07096347 (5 worldwide citation)

The instruction pipeline of a processor, which includes execution circuitry and instruction sequencing logic, receives a stream of instructions including a pipeline interlocking test instruction. The processor includes pipeline control logic that, responsive to receipt of the test instruction, inter ...


10
David R Dreitzler, Charles R Moore: Ramp current apparatus and method of sensitivity testing. The United States of America represented by the Secretary of the Army, Nathan Edelberg, Robert P Gibson, Jack W Voigt, January 13, 1976: US03931730 (4 worldwide citation)

A ramp current method of sensitivity testing allows a dynamic record to be btained of the current, voltage, and energy, as well as resistance and instantaneous power necessary to fire electroexplosive devices. This method is most valuable in that useful information is gained from each firing and thu ...