1
Lam Q Dang, Charles P Geer, Merle E Houdek, Eugene R Jones, Frank G Soltis, John A Soyring, Thomas M Walker: Apparatus for compressing and buffering data. International Business Machines Corporation, Donald F Voss, Bradley A Forrest, March 4, 1986: US04574351 (120 worldwide citation)

Apparatus for compressing and buffering large amounts of data, transferring the buffered data to a slower speed storage device and controlling the stopping and starting of the central processing unit (CPU) is provided for a virtual storage computer system where the data is collected in real time; th ...


2
Richard G Eikill, Steven J Finnes, Charles P Geer, Quentin G Schmierer: Memory card resident diagnostic testing. International Business Machines Corporation, December 28, 1993: US05274648 (29 worldwide citation)

A data processing network includes multiple processing devices, multiple memory cards of main storage, and a main storage interface shared by the processors and memory cards. Each of the memory cards includes memory arrays, a hold register for retaining a data pattern stored to the arrays, a compare ...


3
Charles P Geer, David W Marquart: Chip identification method for use with scan design systems and scan testing techniques. IBM Corporation, Joan Pennington, J Michael Anglin, Bradley A Forrest, January 7, 1992: US05079725 (24 worldwide citation)

A method and apparatus are provided for uniquely identifying integrated circuit chips adapted for use with scan design systems and scan testing techniques. A predetermined identification number corresponding to each LSI chip to be identified is assigned. Each predetermined identification number has ...


4
John M Borkenhagen, Quentin G Schmierer, Charles P Geer: System and method for automatically configuring translation of logical addresses to a physical memory address in a computer memory system. International Business Machines Corporation, Hugh D Jaeger, November 19, 1991: US05067105 (18 worldwide citation)

A system for altering physical addresses of semiconductor memory cards to locate an error-free portion to provide a contiguous range of storage which is free from errors. The system contains a memory card ID register which stores the physical addresses of memory cards in positions corresponding to l ...


5
Richard G Eikill, Charles P Geer, Sheldon B Levenstein: Fast store-through cache memory. International Business Machines Corporation, Frederick W Niebuhr, J Michael Anglin, April 27, 1993: US05206941 (14 worldwide citation)

A fast store-through cache process is disclosed in connection with multiple processors sharing a main storage memory. Each processor has a cache memory including multiple cache lines, each line associated with an address in main storage. Each cache memory has a cache directory for recording main sto ...


6
Richard G Eikill, Charles P Geer: Memory card refresh buffer. International Business Machines Corporation, Frederick W Niebuhr, J Michael Anglin, March 9, 1993: US05193165 (11 worldwide citation)

A data processing network includes multiple processing devices, one or more memory cards in main storage, and a shared interface for processor access to main storage. Each of the memory cards includes dynamic random access memory arrays which require a periodic refresh pulse. To provide refresh puls ...


7
Steven J Baumgartner, Anthony R Bonaccio, Timothy C Buchholtz, Charles P Geer, Daniel G Young: Phase rotator control test scheme. International Business Machines Corporation, Patterson & Sheridan, August 11, 2009: US07573937 (4 worldwide citation)

Techniques and apparatus for testing phase rotators for detecting defective tap weights are provided. Phase rotator test logic may include a master phase rotator to cycle the phase of a clock signal distributed to operational phase rotators through an entire cycle of phases (e.g., an entire 360 degr ...


8
Charles P Geer: Latency optimized data alignment racheting scheme. International Business Machines Corporation, Patterson & Sheridan, July 7, 2009: US07558893 (2 worldwide citation)

A system, method and apparatus for aligning data sequentially received on multiple single-byte data paths are provided. A sufficient number of bytes received in each channel may be stored (e.g., buffered) and examined to properly match data from each single-byte path. Once matched, the data may be o ...


9
Anthony G Aipperspach, Steven J Baumgartner, Charles P Geer, David P Paulsen, David W Siljenberg, Alan P Wagstaff: Level-shifting latch. International Business Machines Corporation, Wood Herron & Evans, Robert R Williams, January 24, 2017: US09553584

A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input s ...


10
Anthony G Aipperspach, Steven J Baumgartner, Charles P Geer, David P Paulsen, David W Siljenberg, Alan P Wagstaff: Level-shifting latch. International Bueinss Machines Corporation, Wood Herron & Evans, Robert R Williams, July 18, 2017: US09712170

A level-shifting latch circuit for coupling a first circuit in a first voltage domain with a second circuit in a second voltage domain, includes an input node to receive an input signal provided by the first circuit, and an output node to output a level-shifted signal, corresponding with the input s ...