1
S Ram Ramaswamy, Charles N Alcorn, Arnett J Brown III, Tatia E Butts: Method for providing a fill pattern for an integrated circuit design. Bae Systems Information and Electronic Systems Integration, Daniel J Long, Antony P Ng, Bracewell & Patterson L, August 19, 2003: US06609235 (193 worldwide citation)

A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be pla ...


2
Nadim Haddad, Charles N Alcorn, Jonathan Maimon, Leonard R Rockett, Scott Doyle: Method for fabricating resistors within semiconductor integrated circuit devices. BAE Systems Information and Electronic Systems Integration, Daniel J Long, Antony P Ng, Bracewell & Patterson L, April 6, 2004: US06717233 (16 worldwide citation)

A method for fabricating resistors within a semiconductor integrated circuit device is disclosed. A resistor is fabricated by first depositing a passivation layer on a semiconductor substrate having multiple transistors previously formed thereon. Next, a first contact window and a second contact win ...


3
Thomas J McIntyre, Charles N Alcorn: Feedback controlled photonic frequency selection circuit. Bae Systems Information And, Electronic Systems Integration, December 30, 2004: US20040264834-A1

A photonic circuit with the ability to precisely select a frequency is disclosed. The temperature of a resonator in the circuit is monitored by a sensor. Data regarding the resonator's temperature is transmitted to a processor. The processor either energizes or varies the amount of current to a heat ...


4
S Ram Ramaswamy, Charles N Alcorn, Arnett J Brown, Tatia B Butts: Method for providing a fill pattern for an integrated circuit design. BAE Systems, Bracewell & Patterson, December 26, 2002: US20020199162-A1

A method for providing a fill pattern for integrated circuit designs is disclosed. A keepout file having keepout data is generated from a chip design layout file having chip design layout data. The keepout file includes a map of areas of an integrated circuit design where fill patterns cannot be pla ...


5
Thomas J McIntyre, Charles N Alcorn, Matthew A Gregory: Method and apparatus for verifying stitching accuracy of stitched chips on a wafer. November 24, 2011: US20110287367-A1

A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a w ...