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Charles J Stancil, Jeffrey C Stevens: Computer fan speed system to reduce audible perceptibility of fan speed changes. Hewlett Packard Development Company, July 29, 2003: US06601168 (36 worldwide citation)

A fan speed controller for a computer system that calculates an internal central processing unit temperature and, in response to target fan speeds communicated over a system management bus, slowly adjusts the computer system fan speed such that audible noise associated with the fan speed change is n ...


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Charles J Stancil: Host I.sup.2 C controller for selectively executing current address reads to I.sup.2 C EEPROMs. Compaq Computer Corporation, Pravel Hewitt & Kimball, April 27, 1999: US05897663 (36 worldwide citation)

A computer system having a bridge and I.sup.2 C EEPROMs is provided with a host I.sup.2 C controller implemented in the bridge for accelerating the reading of the I.sup.2 C EEPROMs. The host I.sup.2 C controller accelerates the reading of I.sup.2 C EEPROMs by executing current address reads of the I ...


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Jens K Ramsey, Jeffrey C Stevens, Michael E Tubbs, Charles J Stancil: Circuit for placing a cache memory into low power mode in response to special bus cycles executed on the bus. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, September 22, 1998: US05813022 (31 worldwide citation)

A circuit for placing an external or L2 cache memory into low power mode in response to certain special cycles executed by the microprocessor. In particular, the special cycles are the stop grant acknowledge special cycle and the halt special cycle. The microprocessor executes the stop grant acknowl ...


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Charles J Stancil: System board with consolidated EEPROM module. Compaq Computer Corporation, Michael F Heim, Jonathan M Harris, Conley Rose & Tayon P C, August 7, 2001: US06272584 (27 worldwide citation)

A computer system is provided with a non-volatile memory module that is shared by a plurality of system components during system initialization. In one embodiment, the computer system comprises a processor for executing program instructions, a memory device for storing data and program instructions, ...


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Charles J Stancil: Desktop computer having enhanced motherboard/riser card assembly configuration. Compaq Computer Corporation, Konneker & Smith P C, October 5, 1999: US05963431 (27 worldwide citation)

A desktop computer system is provided in which a motherboard is mounted within a computer chassis atop a tray which is rearwardly slidable out of a rear wall opening in the chassis to provide access to the motherboard. I/O cables are coupled to I/O connectors mounted on a rear end edge of the mother ...


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Fernando Concha, Charles J Stancil: Error checking and correcting for read-modified-write operations. International Business Machines Corporation, November 28, 1989: US04884271 (25 worldwide citation)

Error detection and correction logic is interposed between a 16-bit CPU and a data storage unit with a 32-bit word size and single bit error correction and double bit error detection (ECC) code bits. During each CPU Read cycle, a full word and its ECC bits are read from storage; and a selected 16 da ...


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Charles J Stancil: Computer system with system ROM including serial-access PROM coupled to an auto-configuring memory controller and method of shadowing BIOS code from PROM. Compaq Computer Corporation, Akin Gump Strauss Hauer & Feld L, September 14, 1999: US05951685 (21 worldwide citation)

A computer system having a processor is provided with a memory controller serially coupled to a serial-access programmable read-only-memory ROM (PROM) through a serial PROM interface of the controller. A random-access memory controller randomly accesses the BIOS code in the serial PROM during power- ...


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Charles J Stancil, William M Vaughn, Jeff W Wolford: Non-conforming PCI bus master timing compensation circuit. Compaq Computer Corporation, Pravel Hewitt Kimball & Krieger, September 24, 1996: US05559968 (17 worldwide citation)

A circuit for preventing a non-conforming PCI bus master from performing cycles where the address driven is not provided soon enough for receiving circuitry to latch the address. The circuit modifies the bus grant signal to force the non-conforming PCI bus master to temporarily release the bus inste ...


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Charles J Stancil, James M Mann, Brant W Jones: Administrator controlled architecture for disabling add-in card slots. Compact Computer, Matthew S Anderson, May 16, 2000: US06065081 (15 worldwide citation)

A system and method for disabling add-in card slots (e.g. PCI or ISA) in a computer system. The slots may be enabled or disabled, according to the preferred embodiment, only after the user has entered a System Administrator password. This password is stored in a non-volatile memory within the comput ...