1
Tyler A Lowrey, Charles H Dennison: Utilizing atomic layer deposition for programmable device. Ovonyx, Trop Pruner & Hu P C, January 28, 2003: US06511867 (379 worldwide citation)

In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the diel ...


2
Charles H Dennison, Alice T Wang, Patel Kanaiyalal Chaturbhai, Jenn C Chow: Reduced area intersection between electrode and programming element. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 12, 2003: US06605527 (374 worldwide citation)

A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer a ...


3
Charles H Dennison, Guy C Wicker, Tyler A Lowrey, Stephen J Hudgens, Chien Chiang, Daniel Xu: Reduced area intersection between electrode and programming element. Ovonyx, Trop Pruner & Hu P C, January 6, 2004: US06673700 (370 worldwide citation)

A method comprising forming a sacrificial layer over less than the entire portion of a contact area on a substrate, the sacrificial layer having a thickness defining an edge over the contact area, forming a spacer layer over the spacer, the spacer layer conforming to the shape of the first sacrifici ...


4
Tyler A Lowrey, Randal W Chance, D Mark Durcan, Ruojia Lee, Charles H Dennison, Yauh Ching Liu, Pierre C Fazan, Fernando Gonzalez, Gordon A Haller: Process for fabricating a DRAM array having feature widths that transcend the resolution limit of available photolithography. Micron Technology, Angus C Fox III, Stanley N Protigal, May 7, 1991: US05013680 (283 worldwide citation)

A process for creating a DRAM array having feature widths that transcend the resolution limit of the employed photolithographic process using only five photomasking steps. The process involves the following steps: creation of a half-pitch hard-material mask that is used to etch a series of equidista ...


5
Charles H Dennison: Phase change memory device on a planar composite layer. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 1, 2004: US06744088 (252 worldwide citation)

Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include an electrode, an adhesive material, an insulating material between the electrode and the adhesive material, wherein a p ...


6
Brian G Johnson, Charles H Dennison: Phase change memory. Intel Corporation, Tony M Martinez, September 14, 2004: US06791102 (252 worldwide citation)

Briefly, in accordance with an embodiment of the invention, a phase change memory and a method to manufacture a phase change memory is provided. The phase change memory may include a phase change material having a bottom portion, a lateral portion, and a top portion. The phase change memory may furt ...


7
Charles H Dennison: Method for fabrication of close-tolerance lines and sharp emission tips on a semiconductor wafer. Micron Technology, Hopkins French Crockett Springer & Hoopes, July 19, 1994: US05330879 (175 worldwide citation)

A method for fabricating submicron lines over a semiconductor material by creating a narrow hard mask over the material using a narrow void-producing process. The narrow void is thus used as a mask to form lines that are narrower than those that can be produced by current lithography techniques. The ...


8
Charles H Dennison, Aftab Ahmad: Method of forming a bit line over capacitor array of memory cells. Micron Semiconductor, Wells St John Roberts Gregory & Matkin, August 16, 1994: US05338700 (165 worldwide citation)

A method of forming a bit line over capacitor array of memory cells includes providing first conductive material pillars within first contact openings downwardly to active (source/drain) areas for ultimate connection with bit lines. A covering layer of insulating material is provided over the first ...


9
Charles H Dennison: Reduced mask CMOS process for fabricating stacked capacitor multi-megabit dynamic random access memories utilizing single etch stop layer for contacts. Micron Technology, Dorr Carson Sloan & Peterson, March 8, 1994: US05292677 (153 worldwide citation)

An etch stop layer is deposited on a DRAM wafer after formation of the PMOS and NMOS transistors and A.A's. After deposition of oxide 1, a first mask and etch process is used to form the capacitor container and remove the oxide 1 and etch stop at the future poly 1 and cell poly contacts. After depos ...


10
Charles H Dennison: Method of forming a bit line over capacitor array of memory cells. Micron Technology, Wells St John Roberts Gregory & Matkin, March 28, 1995: US05401681 (146 worldwide citation)

A method of forming a bit line over capacitor array of memory cells includes, a) providing an array of word lines; b) providing active areas about the word lines to define an array of memory cell FETs; c) providing a layer of electrically insulating material over the word lines and active areas; d) ...



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