1
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ron Kaschak, Whitham Curtis & Whitham, December 14, 1999: US06002177 (250 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...


2
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ron Kaschak, McGuirewoods, May 22, 2001: US06236115 (213 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...


3
Michael Anthony Gaynes, Alan James Emerick, Viswanadham Puligandla, Charles Gerard Woychik, Jerzy Maria Zalesinski: High density integrated circuit packaging with chip stacking and via interconnections. International Business Machines Corporation, Ronald A Kaschak, McGuireWoods, February 13, 2001: US06187678 (188 worldwide citation)

Chip stacks with decreased conductor length and improved noise immunity are formed by laser drilling of individual chips, such as memory chips, preferably near but within the periphery thereof, and forming conductors therethrough, preferably by metallization or filling with conductive paste which ma ...


4
William Rena LaFontaine Jr, Paul Allen Mescher, Charles Gerard Woychik: Semiconductor chip package having chip-to-carrier mechanical/electrical connection formed via solid state diffusion. International Business Machines Corporation, William N Hogg, October 10, 2000: US06130476 (42 worldwide citation)

A method for joining a semiconductor integrated circuit chip in a flip chip configuration, via solder balls, to solderable metal contact pads, leads or circuit lines on the circuitized surface of an organic chip carrier substrate, as well as the resulting chip package, are disclosed. The inventive m ...


5
Robert Gideon Wodnicki, Rayette Ann Fisher, Charles Gerard Woychik, Shubhra Bansal, Albert Taesung Byun: Large area modular sensor array assembly and method for making the same. General Electric Company, Scott J Asmus, January 1, 2013: US08345508 (40 worldwide citation)

A modular and tileable sensor array with routing in the interposer carrying the signals from the sensors to the integrated circuits. In one embodiment a large area modular sensor array assembly includes one or more tileable modules coupled together. The tileable modules have a plurality of transduce ...


6
Cynthia Susan Milkovich, Mark Vincent Pierson, Charles Gerard Woychik: CTE compensated chip interposer. International Business Machines Corporation, John Jordan, June 4, 2002: US06399892 (37 worldwide citation)

A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. ...


7
Robert Gideon Wodnicki, David Martin Mills, Rayette Ann Fisher, Charles Gerard Woychik: Monitoring or imaging system with interconnect structure for large area sensor array. General Electric Company, Jason K Klindtworth, February 22, 2011: US07892176 (34 worldwide citation)

An ultrasonic monitoring system is formed with a probe unit. In one example an array of transducer cells is arranged in rows and columns formed along a first plane with a first pitch along a first direction. An integrated circuit including an array of circuit cells is formed along a second plane par ...


8
Charles Gerard Woychik, Rayette Ann Fisher, David Martin Mills, Scott Cogan, David Richard Esler, Robert Gideon Wodnicki, Jeffrey Scott Erlbaum: Modular sensor assembly and methods of fabricating the same. General Electric Company, Fletcher Yoder, November 18, 2008: US07451651 (33 worldwide citation)

A modular sensor assembly and methods of fabricating a modular sensor assembly are provided. The modular sensor assembly includes a sensor array coupled to an electronics array in a stacked configuration. The sensor array comprises a plurality of sensor modules, each comprising a plurality of sensor ...


9
Amit K Sarkhel, Charles Gerard Woychik: Lead-free, tin-based multi-component solder alloys. International Business Machines Corporation, Calfee Halter & Griswold, March 24, 1998: US05730932 (23 worldwide citation)

The present invention provides a solder alloy having from about 80-81% tin, from about 2-4% silver, from about 5-6% indium, and from about 10-12% bismuth by weight, and microelectric circuits soldered by this alloy.


10
Cynthia Susan Milkovich, Mark Vincent Pierson, Charles Gerard Woychik: Method of making a CTE compensated chip interposer. International Business Machines Corporation, Lawrence R Fraley, February 11, 2003: US06516513 (20 worldwide citation)

A multilayer CTE compensated chip interposer for connecting a semiconductor chip to a laminate chip carrier. A first dielectric layer, on the chip side of the interposer, is made of a stiff, high elastic modulus, material, such as a ceramic material, with a CTE closely matching the CTE of the chip. ...