1
Charles E Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M Rand, Jerry J Hall: Packet processing system including a policy engine having a classification unit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 5, 2000: US06157955 (516 worldwide citation)

The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets ...


2
Charles E Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M Rand, Jerry J Hall: Programmable system for processing a partitioned network infrastructure. Intel Corporation, Blakely Sokoloff Taylor & Zafman, July 16, 2002: US06421730 (131 worldwide citation)

The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets ...


3
Charles E Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M Rand, Jerry J Hall: Programmable system for processing a partitioned network infrastructure. Intel Corporation, Robert A Greenberg, February 22, 2005: US06859841 (115 worldwide citation)

The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets ...


4
Charles E Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M Rand, Jerry J Hall: Platform permitting execution of multiple network infrastructure applications. Intel Corporation, Blakely Sokoloff Taylor & Zafman, June 4, 2002: US06401117 (96 worldwide citation)

The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets ...


5
Yousef A Khalidi, Glen R Anderson, Stephen A Chessin, Shing I Kong, Charles E Narad, Madhusudhan Talluri: Virtual address to physical address translation cache that supports multiple page sizes. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, December 26, 1995: US05479627 (92 worldwide citation)

A method and apparatus for translating a virtual address to a physical address. A virtual address to be translated has a virtual page offset and a virtual page number. The virtual address to be translated addresses a page of memory. The size of this page is unknown. There are L different possible pa ...


6
Charles E Narad, Zahir Ebrahim, Satyanarayana Nishtala, William C Van Loo, Kevin B Normoyle, Louis F Coffin III, Leslie Kohn: Method and apparatus for reducing power consumption in a computer network without sacrificing performance. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, November 25, 1997: US05692197 (69 worldwide citation)

A method and apparatus for actively managing the overall power consumption of a computer network which includes a plurality of computer systems interconnected to each other. In turn, each computer system has one or more modules. Each computer system of the computer network is capable of independentl ...


7
William C Van Loo, Zahir Ebrahim, Satyanarayana Nishtala, Kevin Normoyle, Leslie Kohn, Louis F Coffin III, Charles E Narad: Memory transaction execution system and method for multiprocessor system having independent parallel transaction queues associated with each processor. Sun Microsystems, Gary S Flehr Hohbach Test Albritton & Herbert Williams, August 12, 1997: US05657472 (56 worldwide citation)

A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two ...


8
Charles E Narad, Sun Den Chen: Bus-to-bus interface for preventing data incoherence in a multiple processor computer system. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, November 22, 1994: US05367695 (46 worldwide citation)

A bus-to-bus interface preserves data coherence between masters and slaves operating within a multiple processor computer system. Two buses are connected via the interface. The first bus connects a number of self-identifying masters. The second bus connects a number of master devices and a number of ...


9
Charles E Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M Rand, Jerry J Hall: Compiler for computer programming language including instruction statements for handling network packets. Intel Corporation, Robert A Greenberg, March 13, 2007: US07191433 (45 worldwide citation)

The present application describes a compiler of a network packet classification programming language that generates code for processors such as an application processor and a processing engine. The programming language includes a variety of instructions including an instruction to declare a network ...


10
Charles E Narad, Kevin Fall, Neil MacAvoy, Pradip Shankar, Leonard M Rand, Jerry J Hall: Multiple consumer-multiple producer rings. Intel Corporation, Robert A Greenberg, September 23, 2003: US06625689 (45 worldwide citation)

The present invention relates to a general-purpose programmable packet-processing platform for accelerating network infrastructure applications which have been structured so as to separate the stages of classification and action. Network packet classification, execution of actions upon those packets ...