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Charles Dennison: METHOD FOR FORMING PHASE-CHANGE MEMORY BIPOLAR ARRAY UTILIZING A SINGLE SHALLOW TRENCH ISOLATION FOR CREATING AN INDIVIDUAL ACTIVE AREA REGION FOR TWO MEMORY ARRAY ELEMENTS AND ONE BIPOLAR BASE CONTACT. Ovonyx, Trop Pruner & Hu P C, July 15, 2003: US06593176 (391 worldwide citation)

The invention relates to a process of forming a phase-change memory device. The process includes forming a salicide structure in peripheral logic portion of the substrate and preventing forming salicide structures in the memory array. The device may include a double-wide trench into which a single f ...


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Charles Dennison: Phase-change memory bipolar array utilizing a single shallow trench isolation for creating an individual active area region for two memory array elements and one bipolar base contact. Ovonyx, Trop Pruner & Hu P C, March 18, 2003: US06534781 (383 worldwide citation)

The invention relates to a process of forming a phase-change memory device. The process includes forming a salicide structure in peripheral logic portion of the substrate and preventing forming salicide structures in the memory array. The device may include a double-wide trench into which a single f ...


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Charles Dennison: Method to selectively increase the top resistance of the lower programming electrode in a phase-change memory. Ovonyx, Trop Pruner & Hu P C, February 24, 2004: US06696355 (172 worldwide citation)

The present invention relates to a process of forming a phase-change memory. A lower electrode is disposed in a first dielectric film. The lower electrode comprises an upper section and a lower section. The upper section extends beyond the first dielectric film. Resistivity in the upper section is h ...


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Charles Dennison: Lower electrode isolation in a double-wide trench. Ovonyx, Trop Pruner & Hu P C, November 11, 2003: US06646297 (171 worldwide citation)

The invention relates to a phase-change memory device. The device includes a double-wide trench into which a single film is deposited but two isolated lower electrodes are formed therefrom. Additionally a diode stack is formed that communicates to the lower electrode. Additionally, other isolated lo ...


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Charles Dennison: Method to selectively remove one side of a conductive bottom electrode of a phase-change memory cell and structure obtained thereby. Intel Corporation, Kenneth M Seddon, November 18, 2003: US06649928 (168 worldwide citation)

The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length ...


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Mark Jost, Charles Dennison: Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells. Micron Technology, Wells St John Roberts Gregory & Matkin P S, February 25, 1997: US05605857 (108 worldwide citation)

A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with on ...


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Mark Helm, Charles Dennison: Semiconductor processing method of forming complementary N-type doped and P-type doped active regions within a semiconductor substrate. Micron Technology, Wells St John Roberts Gregory & Matkin P S, April 29, 1997: US05624863 (108 worldwide citation)

A semiconductor processing method of forming complementary first conductivity type doped and second conductivity type doped active regions within a semiconductor substrate includes, a) providing a semiconductor substrate; b) masking a desired first conductivity type region of the substrate while con ...


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Charles Dennison: Method of forming a bit line over capacitor array of memory cells. Micron Technology, Wells St John Roberts Gregory & Matkin, April 27, 1993: US05206183 (88 worldwide citation)

A method of forming a bit line over capacitor array of memory cells includes providing a first layer of polyimide over word lines. Such layer is then patterned and etched to define storage node circuits. A first layer of conductively doped polysilicon is applied over the first layer of polyimide. A ...


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Mark Jost, Charles Dennison: Array of bit line over capacitor array of memory cells. Micron Technology, Wells St John Roberts Gregory & Matkin P S, January 6, 1998: US05705838 (73 worldwide citation)

A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with on ...


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Mark Jost, Charles Dennison: Method of forming a bit line over capacitor array of memory cells and an array of bit line over capacitor array of memory cells. Micron Technology, Wells St John Roberts Gregory & Matkin P S, December 30, 1997: US05702990 (58 worldwide citation)

A semiconductor memory device includes, a) a semiconductor substrate; b) a field effect transistor gate positioned outwardly of the semiconductor substrate; c) opposing active areas formed within the semiconductor substrate on opposing sides of the gate; d) a capacitor electrically connected with on ...