1
Walford W Ho, Chao Chiang Chen, Yuk Y Yang: Hierarchically-structured programmable logic array and system for interconnecting logic elements in the logic array. Intelligent Logic Systems, Phong K Fenwick & West Truong, October 3, 1995: US05455525 (329 worldwide citation)

A structured logic array is divided into hierarchical levels. At a highest level (the chip level), blocks are interconnected by a system of chip busses. A block interface couples each block to the chip bus system to allow the blocks to communicate with each other. At a lower level, each block includ ...


2
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel, Chao Chiang Chen: Programmable logic device with multi-port memory. Altera Corporation, Quickturn Design Systems, Lyon & Lyon, January 4, 2000: US06011744 (44 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configur ...


3
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel, Chao Chiang Chen: PLD with on-chip memory having a shadow register. Altera Corporation, Quickturn Design Systems, Townsend and Townsend and Crew, March 5, 2002: US06353552 (33 worldwide citation)

Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory ...


4
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel, Chao Chiang Chen: Programmable logic device with multi-port memory. Altera Corporation, Quickturn Design, Townsend and Townsend and Crew, January 4, 2000: US06011730 (19 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configur ...


5
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel, Chao Chiang Chen: FPGA with on-chip multiport memory. Altera Corporation, Quickturn Design Systems, Townsend and Townsend and Crew, November 13, 2001: US06317367 (18 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multiported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multiported memory can be configured ...


6
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel, Chao Chiang Chen: Programmable logic device with multi-port memory. Quickturn Design Systems, Altera Corporation, Lyon & Lyon, November 21, 2000: US06151258 (6 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array ("FPGA"), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configur ...


7
Stephen P Sample, Michael R Butts, Kevin A Norman, Rakesh H Patel, Chao Chiang Chen: Programmable logic device with multi-port memory. Altera Corporation, Quickturn Design Systems, Townsend & Townsend & Crew, April 17, 2001: US06219284 (2 worldwide citation)

An integrated circuit for implementing reconfigurable logic, such as a field programmable gate array (“FPGA”), as described herein has multiple blocks of multi-ported memory. The memory has a plurality of read ports and a plurality of write ports. Each port of the multi-ported memory can be configur ...


8
Kai Keung Chan, David Tsang, Shian Jiun Fu, Chao Chiang Chen: Method and apparatus for facilitating communication between programmable logic circuit and application specific integrated circuit with clock adjustment. Agate Logic, James M Wu, JW Law Group, March 17, 2015: US08981813

A logic processing device, containing an application specific integrated circuit (“ASIC”) and field programmable gate array (“FPGA”), capable of automatically interfacing between ASIC and FPGA is disclosed. The logic processing device, in one aspect, includes a phase adjustment circuit, ASIC, and co ...


9
Stephen Sample, Michael Butts, Kevin Norman, Rakesh Patel, Chao Chiang Chen: PLD with on-chip memory having a shadow. Townsend And Townsend And Crew 015114, August 30, 2001: US20010017793-A1

Methods and apparatus for initializing and determining the contents of a memory block in a programmable logic device. One apparatus includes a logic element, programmably configurable to implement user-defined combinatorial or registered logic functions, and a memory block to store data. The memory ...


10
Chao Chiang Chen, J George Janac: Method of optimizing IC logic performance by static timing based parasitic budgeting. Ronald Craig Fish, October 4, 2007: US20070234266-A1

Increasing need to gain higher performance and lower power in semiconductor chips and field programable gate arrays requires that optimization be done in a constructive manner with respect to physical layout. Increasing perfomance by parasitic budgeting which dictates what parasitics are acceptable ...