Ulrich Klostermann
Chanro Park, Wolfgang Raberg, Ulrich Klostermann: Memory structure and method of manufacture. Infineon Technologies, Atlis Semiconductor, Slater & Matsil L, September 9, 2008: US07423282 (6 worldwide citation)

A solid state electrolyte memory structure includes a solid state electrolyte layer, a metal layer on the solid state electrolyte layer, and an etch stop layer on the metal layer.

Ulrich Klostermann
Ulrich Klostermann, Chanro Park, Wolfgang Raberg: Memory having cap structure for magnetoresistive junction and method for structuring the same. Altis Semiconductor SNC, Infineone Technologies, Dicke Billig & Czaja PLLC, October 13, 2009: US07602032 (4 worldwide citation)

A memory and method of making a memory is disclosed. In one embodiment, the memory includes a cap structure for a magnetoresistive random access memory device including an etch stop layer formed over an upper magnetic layer of a magnetoresistive junction (MTJ/MCJ) layered structure and a hardmask la ...

Gregory Costrini, Frank Findeis, Gill Yong Lee, Chanro Park: Mask schemes for patterning magnetic tunnel junctions. Infineon Technologies, International Business Machines Corporation, Slater & Matsil L, February 21, 2006: US07001783 (21 worldwide citation)

Methods of patterning magnetic tunnel junctions (MTJ's) of magnetic memory devices that avoid shorting magnetic memory cells to upper levels of conductive lines during etching processes. One method involves using a hard mask having two material layers to pattern the lower magnetic material layers of ...

Michael C Gaidis, David W Abraham, Stephen L Brown, Arunava Gupta, Chanro Park, Wolfgang Raberg: Method of patterning a magnetic tunnel junction stack for a magneto-resistive random access memory. International Business Machines Corporation, Infineon Technologies, Daryl K Neff, Margaret A Pepper, May 1, 2007: US07211446 (16 worldwide citation)

A method of patterning a magnetic tunnel junction (MTJ) stack is provided. According to such method, an MTJ stack is formed having a free layer, a pinned layer and a tunnel barrier layer disposed between the free layer and the pinned layer. A first area of the MTJ stack is masked while the free laye ...

Ruilong Xie, Min Gyu Sung, Ryan Ryoung Han Kim, Kwan Yong Lim, Chanro Park: Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products. GLOBALFOUNDRIES, Amerson Law Firm PLLC, June 7, 2016: US09362181 (16 worldwide citation)

One illustrative method disclosed herein includes forming first sacrificial gate structures above a fin for two active gates and a dummy gate, removing the first sacrificial gate structure for the dummy gate so as to define a cavity that exposes the fin while leaving the first sacrificial gate struc ...

Michael C Gaidis, Joachim Nuetzel, Walter Glashauser, Eugene O&apos Sullivan, Gregory Costrini, Stephen L Brown, Frank Findeis, Chanro Park: Recessed metal lines for protective enclosure in integrated circuits. Infineon Technologies, International Business Machines Corporation, Slater & Matsil L, November 2, 2004: US06812141 (14 worldwide citation)

Encapsulating areas of metallization in a liner material, such as Tantalum, Tantalum Nitride, Silicon Carbide allows aggressive or harsh processing steps to be used. These aggresive processing steps offer the possibility of fabricating new device architectures. In addition, by encapsulating the area ...

John H Zhang, Kwan Yong Lim, Steven John Bentley, Chanro Park: Self-aligned gate-first VFETs using a gate spacer recess. GLOBALFOUNDRIES, Ditthavong & Steiner P C, January 3, 2017: US09536793 (8 worldwide citation)

Methods for self-aligned gate-first VFETs using gate-spacer recess and the resulting devices are disclosed. Embodiments include providing a substrate including adjacent transistor regions; forming adjacent and spaced fin-structures each including hardmask over a fin and over a different transistor r ...

Chanro Park, Hoon Kim, Min Gyu Sung: Methods of forming gate structure of semiconductor devices and the resulting devices. GLOBALFOUNDRIES, Amerson Law Firm PLLC, November 17, 2015: US09190488 (5 worldwide citation)

One method disclosed includes forming a replacement gate structure for a device. The method includes forming a gate cavity above a semiconductor substrate. The method further includes forming a first bulk metal layer in the gate cavity above a work function metal layer. The method further includes f ...

Chanro Park, Gill Yong Lee: Method of patterning a magnetic memory cell bottom electrode before magnetic stack deposition. Infineon Technologies, Slater & Matsil L, February 1, 2005: US06849465 (5 worldwide citation)

A method of patterning a bottom electrode for a magnetic memory cell. The bottom electrode is patterned prior to the deposition of the soft layer of the magnetic tunnel junction (MTJ) material stack, preventing the formation of fencing on the sidewalls of the soft layer, which can cause shorts to su ...

Min Gyu Sung, Chanro Park, Hoon Kim, Ruilong Xie: Methods of forming punch through stop regions on FinFET devices on CMOS-based IC products using doped spacers. GLOBALFOUNDRIES, Amerson Law Firm PLLC, November 29, 2016: US09508604 (5 worldwide citation)

One illustrative method disclosed herein includes, among other things, forming a first plurality of fins for a type 1 device and a second plurality of fins for a type 2 device, forming a first counter-doped sidewall spacer structure adjacent the first fins, forming a second counter-doped sidewall sp ...