1
Cecil H Kaplinsky: Memory access controller. Signetics Corporation, Jack E Haken, James J Cannon Jr, May 26, 1987: US04669043 (145 worldwide citation)

The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a tra ...


2
Cecil H Kaplinsky: Programmable logic device. Plug Logic, Thomas Schneck, July 11, 1989: US04847612 (106 worldwide citation)

A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input ...


3
Theodor Mulder, Cecil H Kaplinsky: Configuration control circuit for programmable logic devices. Plus Logic, Thomas Schneck, July 10, 1990: US04940909 (81 worldwide citation)

A configuration control circuit in an integrated circuit device, such as a programmable logic device, having a programmable memory for storing configuration bits and one or more shift registers which are loadable from the memory. The memory is an array of nonvolatile memory cells that can be user pr ...


4
Cecil H Kaplinsky: Programmable CMOS flip-flop emptying multiplexers. Schneck & McHugh, November 17, 1992: US05164612 (69 worldwide citation)

A CMOS flip-flop circuit that includes master and slave inverter latches, a pass transistor for opening and closing access of the master latch input to an input signal D, and a special driver circuit between the master and slave latches to pull the input of the slave latch either up or down dependin ...


5
Cecil H Kaplinsky: Programmable dynamic line-termination circuit. Thomas Schneck, Mark Protsik, March 10, 1998: US05726583 (67 worldwide citation)

A dynamic termination circuit is disclosed that has a plurality of parallel termination elements that respond successively to a signal transition and which are selectively enabled and disabled to provide a desired impedance match with a transmission line. Each termination element includes a first dy ...


6
Cecil H Kaplinsky: Programmable logic device with programmable inverters at input/output pads. Plus Logic, Schneck & McHugh, July 2, 1991: US05028821 (60 worldwide citation)

A programmable logic device having a plurality of functional units, a programmable interconnect matrix for connecting the functional units together, input and output pins coupled to the interconnect matrix, and programmable inverters connected between the pins and conductive lines of the matrix to p ...


7
Craig A MacKenna, Cecil H Kaplinsky: System having a host independent input/output processor for controlling data transfer between a memory and a plurality of I/O controllers. North American Philips Corp Signetics Div, Jack D Slobod, July 14, 1992: US05131081 (58 worldwide citation)

An input/output (I/O) processor and data processing system in which the processor receives and services interrupt request signals from I/O controllers, which requests may be internally or externally coded, and supervises blockwise transfer of data between an external memory associated with a main pr ...


8
Martin Freeman, Cecil H Kaplinsky: Guarded regions for controlling memory access. Signetics, June 30, 1987: US04677546 (58 worldwide citation)

In a virtual memory system, a guarded region allows access to protected code and data without intervention from a processor's operating system by redefining regions of an address space with reference to gates indicating points of entry for those regions. A non-hierarchial access path in the form of ...


9
Cecil H Kaplinsky: Programmable logic device with ganged output pins. Plus Logic, Schneck & McHugh, June 11, 1991: US05023606 (57 worldwide citation)

A programmable logic device architecture having a matrix of smaller functional units, each of which being a programmable logic array, and a set of fixed conductive lines connected to the functional unit inputs and outputs, the conductive lines forming programmable interconnection matrices. The input ...


10
Cecil H Kaplinsky: Clock distribution circuit with active de-skewing. Schneck & McHugh, March 29, 1994: US05298866 (53 worldwide citation)

A clock distribution circuit with multiple clock drivers distributing a clock signal on multiple signal paths has active de-skewing logic circuitry for equalizing the total clock delay to the different clock recipient circuits in a system. The de-skewing logic uses a return path parallel to the outw ...