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Katherina Babich
Deok kee Kim, Kenneth T Settlemyer Jr, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. International Business Machines Corporation, Whitman Curtis Christofferson & Cook PC, Joseph P Abate, March 3, 2009: US07497959 (4 worldwide citation)

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


2
Katherina Babich
Deok kee Kim, Kenneth T Settlemyer, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Thimothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. Whitham Curtis & Christofferson PC, October 23, 2008: US20080261128-A1

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


3
Katherina Babich
Deok kee Kim, Kenneth T Settlemyer, Kangguo Cheng, Ramachandra Divakaruni, Carl J Radens, Dirk Pfeiffer, Timothy Dalton, Katherina Babich, Arpan P Mahorowala, Harald Okorn Schmidt: Methods and structures for protecting one area while processing another area on a chip. International Business Machines Corporation, Whitham Curtis & Christofferson PC, November 17, 2005: US20050255386-A1

Increased protection of areas of a chip are provided by both a mask structure of increased robustness in regard to semiconductor manufacturing processes or which can be removed with increased selectivity and controllability in regard to underlying materials, or both. Mask structures are provided whi ...


4
Lawrence A Clevenger, Louis Lu Chen Hsu, Jack A Mandelman, Carl J Radens: Self-trimming method on looped patterns. International Business Machines Corporation, Richard M Ludwin Esq, McGinn & Gibb PLLC, October 14, 2003: US06632741 (203 worldwide citation)

A method of self-trimming pattern, includes forming a pattern containing a plurality of regular or irregular features within a first material deposited on a substrate, depositing a conformal layer of second material, and etching the second material to form spacers of the second material along the si ...


5
Carl J Radens, Gary B Bronner, Tze chiang Chen, Bijan Davari, Jack A Mandelman, Dan Moy, Devendra K Sadana, Ghavam Ghavami Shahidi, Scott R Stiffler: Silicon-on-insulator vertical array device trench capacitor DRAM. International Business Machines Corporation, H Daniel Schnurmann, May 20, 2003: US06566177 (162 worldwide citation)

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell and array and method of manufacture. The memory cell includes a trench storage capacitor connected by a self aligned buried strap to a vertical access transistor. A buried oxide layer isolates an SOI layer from a silicon substrate ...


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Jack A Mandelman, Oleg Gluschenkov, Carl J Radens: Structure and method for MOSFET with metallic gate electrode. International Business Machines Corporation, Tiffany L Townsend Esq, Scully Scott Murphy & Presser, April 13, 2004: US06720630 (65 worldwide citation)

A method of forming a metal oxide semiconductor field effect transistor (MOSFET) having a metallic gate electrode that is protected with hanging sidewall spacers during a subsequent gate oxidation process is provided. A semiconductor structure formed by the inventive method is also provided. Specifi ...


8
Rama Divakaruni, Louis C Hsu, Rajiv V Joshi, Carl J Radens: High performance FET with elevated source/drain region. International Business Machines, Law Office of Charles W Peterson Jr, Louis J Percello, March 8, 2005: US06864540 (58 worldwide citation)

The invention includes a field effect transistor (FET) on an insulator layer, and integrated circuit (IC) on SOI chip including the FETs and a method of forming the IC. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin si ...


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Carl J Radens, Gary B Bronner, Tze chiang Chen, Bijan Davari, Jack A Mandelman, Dan Moy, Devendra K Sadana, Ghavam Ghavami Shahidi, Scott R Stiffler: Silicon-on-insulator vertical array DRAM cell with self-aligned buried strap. International Business Machines Corporation, H Daniel Schnurmann, July 30, 2002: US06426252 (46 worldwide citation)

A silicon on insulator (SOI) dynamic random access memory (DRAM) cell, array and method of manufacture. The memory cell includes a vertical access transistor above a trench storage capacitor in a layered wafer. A buried oxide (BOX) layer formed in a silicon wafer isolates an SOI layer from a silicon ...



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