1
Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven, LAM Christine S, May 26, 2006: WO/2006/055482 (11 worldwide citation)

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


2
Bill Colin S, Cai Wei Daisy: Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices. Spansion, Bill Colin S, Cai Wei Daisy, JAIPERSHAD Rajendra, December 7, 2006: WO/2006/130438 (9 worldwide citation)

In the present method of programming and erasing the resistive memory devices (30) of an array thereof, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices (30) whose state is to be changed from the previous state the ...


3
Bill Colin S, Cai Wei Daisy: Temperature compensation of thin film diode voltage threshold in memory sensing circuit. Spansion, Bill Colin S, Cai Wei Daisy, DRAKE Paul S, September 28, 2006: WO/2006/102391 (7 worldwide citation)

Systems and methodologies are provided for temperature compensation of thin film diode voltage levels in memory sensing circuits. The subject invention includes a temperature sensitive bias circuit (408) and an array core (500) with a temperature variable select device (430). The array core (500) ca ...


4
Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, August 1, 2007: GB2434694-A

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


5
Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, chengwei wangjin yang, October 17, 2007: CN200580039025

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


6
Bill Colin S, Cai Wei Daisy: Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices. Spansion, gebo, April 30, 2008: CN200680015533

In the present method of programming and erasing the resistive memory devices (30) of an array thereof, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices (30) whose state is to be changed from the previous state the ...


7
Fang Tzu Ning, Bill Colin S, Cai Wei Daisy, Gaun David, Gershon Eugene: Program/erase waveshaping control to increase data retention of a memory cell. Spansion, gebo, December 3, 2008: CN200680027637

System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across ...


8
Fang Tzu Ning, Bill Colin S, Cai Wei Daisy, Gaun David, Gershon Eugene: Program/erase waveshaping control to increase data retention of a memory cell. Spansion, December 16, 1980: EP1911035-A2

System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across ...


9
Bill Colin S, Cai Wei Daisy: Page buffer architecture for programming, erasing and reading nanoscale resistive memory devices. Spansion, February 6, 2008: EP1883929-A1

In the present method of programming and erasing the resistive memory devices of an array thereof, upon a single command, high current is provided in both the program and erase functions to program and erase only those memory devices whose state is to be changed from the previous state thereof.


10
Fang Tzu Ning, Bill Colin S, Cai Wei Daisy, Gaun David, Gershon Eugene: Program/erase waveshaping control to increase data retention of a memory cell. Spansion, Fang Tzu Ning, Bill Colin S, Cai Wei Daisy, Gaun David, Gershon Eugene, JAIPERSHAD Rajendra, February 8, 2007: WO/2007/015864

System(s) and method(s) of improving and controlling memory cell data retention are disclosed. A particular pulse width and magnitude is generated and applied to a memory cell made of at least two electrodes with a controllably conductive media between the at least two electrodes. The current across ...



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