1
Byron T Ahlburn, Thomas R Seha: Method of forming a multilevel dielectric. Texas Instruments Incorporated, Robby Holland, Leo Heiting, Richard Donaldson, March 4, 1997: US05607773 (38 worldwide citation)

A method of forming a planar dielectric layer over an interconnect pattern which requires fewer processing steps and has a lower dielectric constant than is obtained in the prior art. The method comprises providing a substrate having an electrical interconnect pattern thereon, forming a first layer ...


2
Don L Kendall, Byron T Ahlburn, Klaus C Wiemer: Discrete, fixed-value capacitor. Texas Instruments Incorporated, Harold Levine, James T Comfort, Gary C Honeycutt, March 29, 1977: US04015175 (16 worldwide citation)

An axial-lead fixed-value capacitor comprising a metal-nitride-oxide-silicon chip in a standard diode package has been fabricated, having capacitance values in the 10 to 1000 pico-farad range. The device features a beveled-edge configuration which contributes to a low leakage current and also facili ...


3
Don L Kendall, Byron T Ahlburn, Klaus C Wiemer: Discrete, fixed-value capacitor. Texas Instruments Incorporated, James T Comfort, Gary C Honeycutt, August 1, 1978: US04104697 (9 worldwide citation)

An axial-lead fixed-value capacitor comprising a metal-nitride-oxide-silicon chip in a standard diode package has been fabricated, having capacitance values in the 10 to 1000 pico-farad range. The device features a beveled-edge configuration which contributes to a low leakage current and also facili ...


4
Byron T Ahlburn: Composite dielectric passivation of high density circuits. Texas Instruments Incorporated, Gary Honeycutt, Rene Grossman, Richard Donaldson, July 22, 1997: US05650359 (8 worldwide citation)

A composite dieletric film for final passivation of an integrated circuit. First, plasma-enhanced TEOS oxide is deposited to a thickness of 2000 .ANG., followed by thermal O.sub.3 -TEOS oxide to a thickness of 8000 .ANG., and then silicon nitride to a thickness of 10,000 .ANG..


5
Shawn T Walsh, John E Campbell, James B Friedmann, Thomas M Parrill, Der&apos E Jan, Joshua J Robbins, Byron T Ahlburn, Sue Ellen Crank: Method for trench isolation of semiconductor devices. Texas Instruments Incorporated, David Denker, Wade James Brady III, Frederick J Telecky Jr, May 8, 2001: US06228741 (2 worldwide citation)

A method is given for removing excess oxide from active areas after shallow trench isolation, without the use of chemical-mechanical polishing. A nitride mask protects active areas during the etch of isolation trenches. The trenches are filled with oxide, using high density plasma deposition, which ...


6
Shawn T Walsh, John E Campbell, James B Freedman, Thomas M Parlile, Dell E Jan, Joshua J Robins, Byron T Ahlburn, Sue Elen Crank: Method of forming trench isolators of transistor, without using chemical-mechanical polishing method. Texas Instr &Lt Ti&Gt, October 15, 1999: JP1999-284064

PROBLEM TO BE SOLVED: To enable the use of the standard treating process and lower the manufacturing cost, by carefully executing the sequence of deposition and etching, a good process providing a far better uniformity than the chemical- mechanical polishing. SOLUTION: A nitride layer 20 is deposite ...


7
Marsden Mary H, Byron T Ahlburn, Karen G Erz: Forming method of flat dielectric layer and multilayered wiring pattern. Texas Instr &Lt Ti&Gt, October 3, 1997: JP1997-260384

PROBLEM TO BE SOLVED: To realize the flattening of an IDL film, by using HSQ.SOG and conformal PETEOS for submicron gaps of vias, wirings, etc., which have sputtered metal wirings. SOLUTION: A part of a semiconductor device constists of a silicon substrate 52 as the lower layer of a dielectric layer ...