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Paton Eric N, Adem Ercan, Bertrand Jacques J, Besser Paul R, Buynoski Matthew S: Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing. Advanced Micro Devices, May 11, 2003: TW531792 (2 worldwide citation)

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance ...


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Paton Eric N, Adem Ercan, Bertrand Jacques J, Besser Paul R, Buynoski Matthew S, Foster John Clayton, King Paul L, Kluth George Jonathan, Ngo Minh Van, Woo Christy Mei Chu: Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing. Advanced Micro Devices, December 31, 2003: GB2390224-A (1 worldwide citation)

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance ...


3
Tabery Cyrus E, Ahmed Shibly S, Buynoski Matthew S, Dakshina Murphy Srikanteswara, Krivokapic Zoran, Wang Haihong, Yang Chih Yuh, Yu bin: Self aligned damascene gate. Advanced Micro Devices, Tabery Cyrus E, Ahmed Shibly S, Buynoski Matthew S, Dakshina Murphy Srikanteswara, Krivokapic Zoran, Wang Haihong, Yang Chih Yuh, Yu bin, sDRAKE PAUL S, May 26, 2005: WO/2005/048339 (1 worldwide citation)

A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin (310) in the fin area, and forming a mask (320) in the fin area. The method further includes etching the mask (320 ...


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Buynoski Matthew S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas H: Self assembly of conducting polymer for formation of polymer memory cell. Advanced Micro Devices, Buynoski Matthew, S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas H, sDRAKE Paul S, May 6, 2005: WO/2005/041319 (1 worldwide citation)

The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer (22) self assembles relative to a conductive electrode (26). The process affords self-assembly such that a sho ...


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Buynoski Matthew S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas: Self assembly of conducting polymer for formation of polymer memory cell. Advanced Micro Devices, August 16, 2006: GB2423174-A

The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer (22) self assembles relative to a conductive electrode (26). The process affords self-assembly such that a sho ...


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Tripsas Nicholas, Buynoski Matthew S, Pangrle Suzette, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, April 19, 2006: GB2419231-A

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


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Tabery Cyrus E, Ahmed Shibly S, Buynoski Matthew S, Dakshina Murphy Srikanteswara, Krivokapic Zoran, Wang Haihong, Yu bin, Yang Chih Yuh: Self aligned damascene gate. Advanced Micro Devices, September 27, 2006: GB2424517-A

A method for forming a metal-oxide semiconductor field-effect transistor (MOSFET) (200) includes patterning a fin area, a source region, and a drain region on a substrate, forming a fin (310) in the fin area, and forming a mask (320) in the fin area. The method further includes etching the mask (320 ...


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Paton Eric N, Adem Ercan, Bertrand Jacques J, Besser Paul R, Buynoski Matthew S, Foster John Clayton, King Paul L, Kluth George Jonathan, Ngo Minh Van, Woo Christy Mei Chu: Method of forming nickel silicide using a one-step rapid thermal anneal process and backend processing. Advanced Micro Devices, September 10, 2003: EP1342260-A1

A self-aligned silicide process that can accommodate a low thermal budget and form silicide regions (64, 66) of small dimensions in a controlled reaction. In a first temperature treatment, nickel metal or nickel alloy (52) is reacted with a silicon material (46) to form at least one high resistance ...



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