1
Maxwell C Gilliland, Burton J Smith, Gary L Ferguson: Concurrent task and instruction processor and method. Denelcor, O Rourke & Harris, October 21, 1980: US04229790 (123 worldwide citation)

A processor and method for concurrent processing of tasks and instructions are disclosed. The processor is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units, but avoids precedence constraint penalties. Task and inst ...


2
Gail A Alverson, Burton J Smith, Laurence S Kaplan, Mark L Niehaus: Debugging techniques in a multithreaded environment. Cray, Perkins Coie, November 12, 2002: US06480818 (76 worldwide citation)

A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a breakpoint instruction does not need to be ret ...


3
Gail A Alverson, Charles David Callahan II, Simon H Kahan, Brian D Koblenz, Allan Porterfield, Burton J Smith: Detecting access to a memory location in a multithreaded environment. Cray, Perkins Coie, July 7, 2009: US07558910 (56 worldwide citation)

Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, dem ...


4
Gail A Alverson, Charles David Callahan II, Simon H Kahan, Brian D Koblenz, Allan Porterfield, Burton J Smith: Synchronization techniques in a multithreaded environment. Cray, Perkins Coie, March 1, 2005: US06862635 (51 worldwide citation)

Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, dem ...


5
Gail A Alverson, Burton J Smith, Laurence S Kaplan, Mark L Niehaus: Debugging techniques in a multithreaded environment. Cray, Perkins Coie, January 25, 2005: US06848097 (33 worldwide citation)

A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a breakpoint instruction does not need to be ret ...


6
Gail A Alverson, Charles David Callahan II, Simon H Kahan, Brian D Koblenz, Allan Porterfield, Burton J Smith: Restricting access to memory in a multithreaded environment. Cray, Perkins Coie, January 16, 2007: US07165150 (25 worldwide citation)

Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, dem ...


7
Gail A Alverson, Charles David Callahan II, Simon H Kahan, Brian D Koblenz, Allan Porterfield, Burton J Smith: Synchronization techniques in a multithreaded environment. Cray, Perkins Coie, March 8, 2011: US07904685 (24 worldwide citation)

Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support for a thread blocked in a word, dem ...


8
Brian D Koblenz, Allan Porterfield, Burton J Smith: Method and system for memory allocation in a multiprocessing environment. Cray, Perkins Coie, March 5, 2002: US06353829 (21 worldwide citation)

A method and system for allocating memory. The computer system on which the memory allocation system executes may support the simultaneous execution of multiple threads. Under control of a thread, the memory allocation system first identifies a bin associated with blocks (“lockers”) of memory large ...


9
Andrew S Kopser, Burton J Smith: Adjustable data delay using programmable clock shift. Cray, Seed IP Law Group PLLC, September 30, 2003: US06629250 (20 worldwide citation)

A circuit for electronically matching and synchronizing the receipt of data on transmission lines between two circuits. Data is transmitted from a sending circuit to a receiving circuit on transmission lines between the two circuits. A system clock is also provided to the receiving circuit to synchr ...


10
Gail A Alverson, Charles David Callahan II, Susan L Coatney, Brian D Koblenz, Richard D Korry, Burton J Smith: Deferred task swapping in a multithreaded environment. Cray, Perkins Coie, May 19, 2009: US07536690 (19 worldwide citation)

A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads executing on a single processor. The ta ...