1
Quinn A Jacobson, Hong Wang, John Shen, Gautham N Chinya, Per Hammarlund, Xiang Zou, Bryant Bigbee, Shivnandan D Kaushik: Primitives to enhance thread-level speculation. Intel Corporation, David P McAbee, February 1, 2011: US07882339 (31 worldwide citation)

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an ...


2
Gautham N Chinya, Hong Wang, Xiang Zou, James Paul Held, Prashant Sethi, Trung Diep, Anil Aggarwal, Baiju V Patel, Shiv Kaushik, Bryant Bigbee, John Shen, Richard A Hankins, John L Reid: Mechanism to emulate user-level multithreading on an OS-sequestered sequencer. Intel Corporation, Caven & Aghevli, October 5, 2010: US07810083 (13 worldwide citation)

Method, apparatus and system embodiments to provide user-level creation, control and synchronization of OS-invisible “shreds” of execution via an abstraction layer for a system that includes one or more sequencers that are sequestered from operating system control. For at least one embodiment, the a ...


3
Hong Wang, Gautham N Chinya, Richard A Hankins, Shivnandan D Kaushik, Bryant Bigbee, John Shen, Per Hammarlund, Xiang Zou, Jason W Brandt, Prashant Sethi, Douglas M Carmean, Baiju V Patel, Scott Dion Rodgers, Ryan N Rakvic, John L Reid, David K Poulsen, Sanjiv M Shah, James Paul Held, James Charles Abel: Sequencer address management. Intel Corporation, David P McAbee, June 22, 2010: US07743233 (12 worldwide citation)

Disclosed are embodiments of a system, methods and mechanism for management and translation of mapping between logical sequencer addresses and physical or logical sequencers in a multi-sequencer multithreading system. A mapping manager may manage assignment and mapping of logical sequencer addresses ...


4
Vincent J Zimmer, Bryant Bigbee, Andrew J Fish, Mark S Doran: Providing a secure execution mode in a pre-boot environment. Intel Corporation, Trop Pruner & Hu P C, July 5, 2011: US07974416 (10 worldwide citation)

In one embodiment, the present invention includes a method to establish a secure pre-boot environment in a computer system; and perform at least one secure operation in the secure environment. In one embodiment, the secure operation may be storage of a secret in the secure pre-boot environment.


5
Xiang Zou, Hong Wang, Scott Dion Rodgers, Darrell D Boggs, Bryant Bigbee, Shivanandan Kaushik, Anil Aggarwal, Ittai Anati, Doron Orenstein, Per Hammarlund, John Shen, Larry O Smith, James B Crossland, Chris J Newburn: Programmable event driven yield mechanism which may activate service threads. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 7, 2010: US07849465 (8 worldwide citation)

Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be ...


6
Gautham Chinya, Hong Wang, Richard A Hankins, Shivnandan D Kaushik, Bryant Bigbee, John Shen, Prashant Sethi, Baiju V Patel, John L Reid: Transparent support for operating system services for a sequestered sequencer. Intel Corporation, Caven & Aghevli, August 20, 2013: US08516483 (5 worldwide citation)

Operating system services are transparently triggered for thread execution resources (“sequencers”) that are sequestered from view of the operating system. A “surrogate” thread that is managed by, and visible to, the operating system is utilized to acquire OS services on behalf of a sequestered sequ ...


7
Bryant Bigbee, Kenneth S Reneris, Shivnandan D Kaushik: Maintaining extended and traditional states of a processing unit in task switching. Intel Corporation, Blakley Sokoloff Taylor & Zafman, February 25, 2003: US06526431 (5 worldwide citation)

The present invention is a method and apparatus for switching first and second tasks in an operating system. The first and second tasks each have first and second traditional states and first and second extended states, in a processing unit. The method comprises: (a) saving the first traditional and ...


8
Francis X McKeen, Lawrence O Smith, Benjamin Crawford Chaffin, Michael P Cornaby, Bryant Bigbee: Mechanism to handle events in a machine with isolated execution. Intel Corporation, Blakely Sokoloff Taylor & Zafman, September 7, 2010: US07793111 (3 worldwide citation)

A platform and method for secure handling of events in an isolated environment. A processor executing in isolated execution “IsoX” mode may leak data when an event occurs as a result of the event being handled in a traditional manner based on the exception vector. By defining a class of events to be ...


9
Gautham Chinya, Hong Wang, Prashant Sethi, Shivnandan Kaushik, Bryant Bigbee, John Shen, Richard Hankins, Xiang Zou, Baiju V Patel, Jason W Brandt, Anil Aggarwal, John L Reid: Apparatus, system, and method for persistent user-level thread. Intel Corporation, Trop Pruner & Hu P C, July 2, 2013: US08479217 (3 worldwide citation)

Embodiments of the invention provide a method of creating, based on an operating-system-scheduled thread running on an operating-system-visible sequencer and using an instruction set extension, a persistent user-level thread to run on an operating-system-sequestered sequencer independently of contex ...


10
Hong Wang, John Shen, Ed Grochowski, James Paul Held, Bryant Bigbee, Shivnandan D Kaushik, Gautham Chinya, Xiang Zou, Per Hammarlund, Xinmin Tian, Anil Aggarwal, Scott Dion Rodgers, Prashant Sethi, Baiju V Patel, Richard Andrew Hankins: Mechanism for instruction set based thread execution on a plurality of instruction sequencers. Intel Corporation, Blakely Sokoloff Taylor & Zafman, May 6, 2014: US08719819 (3 worldwide citation)

In an embodiment, a method is provided. The method includes managing user-level threads on a first instruction sequencer in response to executing user-level instructions on a second instruction sequencer that is under control of an application level program. A first user-level thread is run on the s ...