41
Mohammed H Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Jeffrey P Rupley II, Edward A Brekelbaum, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 1, 2009: US20090001601-A1

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...


42
Hong Wang, Jamison Collins, John P Shen, Bryan Black, Perry H Wang, Edward T Grochowski, Ralph M Kling: Software-based speculative pre-computation and multithreading. Jan Carol Little, Blakely Sokoloff Taylor & Zafman, October 3, 2002: US20020144083-A1

Speculative pre-computation and multithreading (SP), allows a processor to use spare hardware contexts to spawn speculative threads to very effectively pre-fetch data well in advance of the main thread. The burden of spawning threads may fall on the main thread via basic triggers. The speculative th ...


43
Ryan Rakvic, Youfeng Wu, Bryan Black, John Shen: Cache mechanism. Blakely Sokoloff Taylor & Zafman, September 22, 2005: US20050210197-A1

According to one embodiment a system is disclosed. The system includes a central processing unit (CPU), a first cache memory coupled to the CPU to store only data for vital loads that are to be immediately processed at the CPU, a second cache memory coupled to the CPU to store data for semi-vital lo ...


44
Bryan Black, Murali Annavaram, Paul Reed: Transferring data from stacked memory. Caven & Aghevli, c o INTELLEVATE, September 20, 2007: US20070220207-A1

Methods and apparatus to transfer data from a stacked memory are described. In one embodiment, an interconnect may be utilized to transfer data into a buffer from one or more opened memory pages.


45
Bohuslav Rychlik, Ryan N Rakvic, Edward Brekelbaum, Bryan Black: Predicate register file scoreboarding and renaming. Blakely Sokoloff Taylor & Zafman, July 17, 2003: US20030135713-A1

A method to handle data dependencies in a pipelined computer system. The method includes allocating a plurality of registers, enabling execution of computer instructions concurrently by using the plurality of registers, and tracking and reducing data dependencies in the computer instructions by corr ...


46
Ryan Rakvic, Christopher Wilkerson, Bryan Black, Edward Grochowski, John Shen, Edward Brekelbaum: Method and system to identify slowable instructions. Blakely Sokoloff Taylor & Zafman, July 3, 2003: US20030126412-A1

After an instruction loads data into a register at a first time, the register is monitored to see if it is read in a next clock cycle. When the data is read in a next clock cycle, the instruction is classified as a slowable instruction. An instruction address associated with the instruction is used ...


47
Maxat Touzelbaev, Gamal Refai Ahmed, Yizhang Yang, Bryan Black: Thermal Interface Material with Support Structure. Timothy M Honeycutt Attorney At Law, September 23, 2010: US20100237496-A1

Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support s ...


48
Bryan BLACK, Joseph Seigel: Die stacking, testing and packaging for yield. Advanced Micro Devices, March 10, 2011: US20110057677-A1

A method to test and package dies so as to increase overall yield is provided. The method includes performing a wafer test on a first die and mounting the first die on a package substrate to form a partial package, if the wafer test of the first die is successful. The method further includes perform ...


49
Mohammed Taufique, Derwin Jallice, Donald W McCauley, John P DeVale, Edward A Brekelbaum, Jeffrey P Rupley II, Gabriel H Loh, Bryan Black: Memory array on more than one die. Intel Bstz, Blakely Sokoloff Taylor & Zafman, June 17, 2010: US20100149849-A1

For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital sign ...


50
Seth Prejean, Dales Kent, Ronnie Brandon, Gamal Refai Ahmed, Michael Z Su, Michael Bienek, Joseph Siegel, Bryan Black: Semiconductor chip with thermal interface tape. February 23, 2012: US20120043539-A1

A method of manufacturing is provided that includes applying a thermal interface tape to a side of a semiconductor wafer that includes at least one semiconductor chip. The thermal interface material tape is positioned on the at least one semiconductor chip. The at least one semiconductor chip is sin ...