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William R Wheeler, Bradley Burres, Matthew J Adiletta, Gilbert Wolrich: SDRAM controller for parallel processor architecture. Intel Corporation, Fish & Richardson P C, January 3, 2006: US06983350 (32 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


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William R Wheeler, Bradley Burres, Matthew J Adiletta, Gilbert Wolrich: Memory controller for processor having multiple multithreaded programmable units. Intel Corporation, Fish & Richardson P C, September 9, 2008: US07424579 (22 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory con ...


3
William R Wheeler, Bradley Burres, Matthew J Adiletta, Gilbert Wolrich: Memory controllers for processor having multiple programmable units. Intel Corporation, Blakely Sokoloff Taylor & Zafman, November 20, 2012: US08316191 (8 worldwide citation)

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


4
Vinodh Gopal, Shay Gueron, Gilbert Wolrich, Wajdi Feghali, Kirk Yap, Bradley Burres: Instruction-set architecture for programmable Cyclic Redundancy Check (CRC) computations. Intel Corporation, Trop Pruner & Hu P C, June 2, 2015: US09047082 (3 worldwide citation)

A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction ...


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Vinodh Gopal, Shay Gueron, Gilbert Wolrich, Wajdi Feghali, Kirk Yap, Bradley Burres: Instruction-set architecture for programmable cyclic redundancy check (CRC) computations. Intel Corporation, Trop Pruner & Hu P C, May 20, 2014: US08732548

A method and apparatus to perform Cyclic Redundancy Check (CRC) operations on a data block using a plurality of different n-bit polynomials is provided. A flexible CRC instruction performs a CRC operation using a programmable n-bit polynomial. The n-bit polynomial is provided to the CRC instruction ...


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Alwyn Dos Remedios, Wajdi K Feghali, Gilbert Wolrich, Bradley Burres: High performance security policy database cache for network processing. Fish & Richardson PC, January 13, 2005: US20050010761-A1

A security policy database cache includes at least one primary table including signature values that indicate that a packet's security policy database information may be in the cache and at least one secondary table including cache entries having a selector, flags, security association information a ...


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Pan Loong Loh, Alwyn Dos Remedios, Bob S Pabla, Walter Gilmore, Wajdi K Feghali, Robert P Ottavi, Bradley Burres: IPSec acceleration using multiple micro engines. Fish & Richardson PC, June 23, 2005: US20050138366-A1

A network forwarding device includes at least one physical interface, a framer and a network processor having multiple processing engines arranged as: a preparation stage provided on a first microengine of a processor having plural microengines the preparation stage to prepare the packet for process ...


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William R Wheeler, Bradley Burres, Matthew J Adiletta, Gilbert Wolrich: Memory controller for processor having multiple programmable units. Intel Corporation a Delaware corporation, Fish & Richardson PC, March 30, 2006: US20060069882-A1

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor-also includes a memory control system that has a first memory con ...


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William R Wheeler, Bradley Burres, Matthew J Adiletta, Gilbert Wolrich: Memory controllers for processor having multiple programmable units. Fish & Richardson PC, January 22, 2009: US20090024804-A1

A parallel hardware-based multithreaded processor is described. The processor includes a general purpose processor that coordinates system functions and a plurality of microengines that support multiple hardware threads. The processor also includes a memory control system that has a first memory con ...


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