1
Om P Agrawal, Bradley A Sharpe Geisler: FPGA with register-intensive architecture. Lattice Semiconductor Corporation, April 11, 2006: US07028281 (170 worldwide citation)

Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A r ...


2
Om P Agrawal, Herman M Chang, Bradley A Sharpe Geisler, Giap H Tran: Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits. Vantis Corporation, Fliesler Dubb Meyer & Lovejoy, August 14, 2001: US06275064 (138 worldwide citation)

A Field Programmable Gate Array (FPGA) device includes a plurality of variable grain blocks (VGBs) and a plurality of interconnect lines for providing program-defined routing of signals between the VGBs. The VGBs include a plurality of L-organized CBBs (configurable logic blocks) having function-pro ...


3
Bai Nguyen, Om P Agrawal, Bradley A Sharpe Geisler, Jack T Wong, Herman M Chang: Efficient interconnect network for use in FPGA device having variable grain architecture. Vantis Corporation, Fliesler Dubb Meyer & Lovejoy, December 19, 2000: US06163168 (133 worldwide citation)

A logic array device has an array of plural interconnect resources including plural lines and plural switchbox areas, with an array of plural Variable Grain Blocks (VGB's) interspersed within the array of plural interconnect resources. The array of plural interconnect resources does not regularly in ...


4
Om P Agrawal, Herman M Chang, Bradley A Sharpe Geisler, Bai Nguyen: FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals. Vantis Corporation, Fliesler Dubb Meyer & Lovejoy, January 30, 2001: US06181163 (105 worldwide citation)

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port ...


5
Benjamin Howard Ashmore Jr, Jeffery Mark Marshall, Bryon Irwin Moyer, John David Porter, Nicholas A Schmitz, Bradley A Sharpe Geisler: Block clock and initialization circuit for a complex high density PLD. Advanced Micro Devices, Forrest E Gunnison, Skjerven Morrill MacPherson Franklin & Friel, September 22, 1998: US05811987 (103 worldwide citation)

A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit incl ...


6
Om P Agrawal, Herman M Chang, Bradley A Sharpe Geisler, Giap H Tran, Bai Nguyen: Synthesis-friendly FPGA architecture with variable length and variable timing interconnect. Vantis Corporation, Gideon Gimlan, Fliesler Dubb Meyer & Lovejoy, October 10, 2000: US06130551 (95 worldwide citation)

A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resourc ...


7
Om P Agrawal, Bradley A Sharpe Geisler: Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices. Advanced Micro Devices, Edward C Kwok, Skjerven Morril MacPherson Franklin & Friel, October 6, 1998: US05818254 (77 worldwide citation)

A hierarchical switch matrix in a very high-density programmable logic device (CPLD) interconnects a multiplicity of programmable logic blocks in the CPLD. A new level of functionality coupled with high speed is provided by the hierarchical switch matrix. The hierarchical switch matrix includes thre ...


8
Bradley A Sharpe Geisler, Jonathan Lin, Radu Barsan: CMOS memory cell with tunneling during program and erase through the NMOS and PMOS transistors and a pass gate separating the NMOS and PMOS transistors. Advanced Micro Devices, Fliesler Dubb Meyer & Lovejoy, July 8, 1997: US05646901 (76 worldwide citation)

An apparatus and method, the apparatus including an NMOS pass gate separating NMOS and PMOS transistors of a CMOS memory cell configured for tunneling during program and erase through the NMOS and PMOS transistors. The additional NMOS pass gate enables the CMOS memory cell to be utilized as a memory ...


9
Om P Agrawal, Bradley A Sharpe Geisler, Nicholas A Schmitz, Bryon I Moyer: Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, May 28, 1996: US05521529 (74 worldwide citation)

A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associate ...


10
Bradley A Sharpe Geisler: Band gap reference using a low voltage power supply. Vantis Corporation, Fliesler Dubb Meyer & Lovejoy, February 29, 2000: US06031365 (72 worldwide citation)

A band gap reference includes an operational amplifier with an output (n23) driving the gate of three current source transistors (501-503). The first current source (501) drives the (+) opamp input (n20) and a transistor (511) functioning as a diode. The second current source (502) drives the (-) op ...