1
Sunil D Mehta, Brad Sharpe Geisler, Steven Fong: Zero-power CMOS non-volatile memory cell having an avalanche injection element. Vantis Corporation, Brinks Hofer Gilson & Lione, February 22, 2000: US06028789 (28 worldwide citation)

A zero-power non-volatile memory cell includes a control element, an avalanche injection element, and a CMOS inverter. A floating-gate electrode is capacitively coupled to the control element, the avalanche injection element, and to the CMOS inverter. The avalanche injection element is arranged, so ...


2
Om P Agrawal, Bai Nguyen, Kuang Chi, Brad Sharpe Geisler, Giap Tran: Scalable serializer-deserializer architecture and programmable interface. Lattice Semiconductor Corporation, MacPherson Kwok Chen & Heid, Greg J Michelson, August 29, 2006: US07098685 (27 worldwide citation)

Systems and methods are disclosed to provide programmable input/output functionality for a programmable logic device. For example, in accordance with one embodiment of the present invention, a programmable interface selectively employs a scalable serializer-deserializer and clock and data recovery c ...


3
Melvin D Chan, Brad Sharpe Geisler: Low-power sense amplifier with feedback. Advanced Micro Devices, Skjerven Morrill MacPherson Franklin & Friel, February 23, 1993: US05189322 (20 worldwide citation)

A sense amplifier is provided for sensing an impedance between two lines. The impedance has two levels. The two lines are, in one embodiment, a product term line and a product term ground line of a programmable logic device. In the amplifier, a pull-up circuit connects one of the two lines to a high ...


4
Henry Law, Brad Sharpe Geisler, Giap Tran, Kiet Truong, Bai Nguyen: Programmable logic device with power-saving architecture. Lattice Semiconductor Corporation, MacPherson Kwok Chen & Heid, Jonathan W Hallman, May 20, 2008: US07376037 (11 worldwide citation)

A programmable logic device (PLD) such as a field programmable gate array (FPGA) has a power-down mode of operation that reduces power consumption during standby or idle periods for the PLD. In one embodiment of the invention, the PLD includes an internal power supply operable to provide power to PL ...


5
Brad Sharpe Geisler, Satwant Singh: Soft error upset hardened integrated circuit systems and methods. Lattice Semiconductor Corporation, Haynes and Boone, June 22, 2010: US07741865 (10 worldwide citation)

In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device m ...


6
Brad Sharpe Geisler, Om P Agrawal, Kiet Truong, Giap Tran, Bai Nguyen: Programmable logic device with a double data rate SDRAM interface. Lattice Semiconductor Corporation, MacPherson Kwok Chen & Heid, Jonathan W Hallman, March 11, 2008: US07342838 (6 worldwide citation)

Within a programmable logic device (PLD), a DDR SDRAM interface for a DDR SDRAM is provided, the DDR SDRAM providing data to the PLD on the rising and falling edges of a DQS signal, the interface including: a first register adapted to capture data associated with the falling edges of the DQS signal; ...


7
Brad Sharpe Geisler, Om P Agrawal, Cindy Lee: Programmable interconnect architecture for programmable logic devices. Lattice Semiconductor Corporation, MacPherson Kwok Chen & Heid, Jonathan W Hallman, August 14, 2007: US07256613 (6 worldwide citation)

In one embodiment of the invention, a programmable logic device (PLD) includes a plurality of programmable logic blocks arrayed in rows and columns, wherein each programmable logic block is coupled to a corresponding vertical routing resource and a corresponding horizontal routing resource, and wher ...


8
Brad Sharpe Geisler, Satwant Singh: Soft error upset hardened integrated circuit systems and methods. Lattice Semiconductor Corporation, January 11, 2011: US07868646 (3 worldwide citation)

In one embodiment, a programmable logic device includes a plurality of configuration cells that store configuration data, wherein the programmable logic device is adapted to provide soft error upset (SEU) protection for the configuration cells that are reprogrammable. The programmable logic device m ...


9
Brad Sharpe Geisler, Timothy Scott Swensen, Sam Tsai, Fabiano Fontana: Dual-port SRAM with bit line clamping. Lattice Semiconductor Corporation, Haynes and Boone, May 28, 2013: US08451679 (3 worldwide citation)

In one embodiment, a memory is provided that includes: a write driver for selectively driving a driven pair of bit lines selected from a plurality of bit line pairs during a write operation; a first stage clamping circuit operable to clamp a pair of internal nodes to a clamping voltage, wherein the ...


10
Brad Sharpe Geisler, Om P Agrawal, Kiet Truong, Giap Tran, Bai Nguyen: Programmable logic device with a multi-data rate SDRAM interface. Lattice Semiconductor Corporation, August 31, 2010: US07787326 (2 worldwide citation)

Within a programmable logic device, a multi-data rate SDRAM interface such as a DDR SDRAM interface includes in one embodiment a DQS clock tree, a slave delay circuit, and a delay-locked loop (DLL). The slave delay circuit is adapted to shift the phase of the DQS signal relative to the phase of data ...