1
Rasekh Rifaat, Boris Lerner: Method, apparatus, and product for use in generating CRC and other remainder based codes. Analog Devices, Wolf Greenfield & Sacks P C, June 28, 2005: US06912683 (17 worldwide citation)

A method, apparatus and product for use in generating a remainder based code generates a plurality of preliminary remainder based codes in response to specified data, and synthesizing a remainder based code for the specified data, in response to the plurality of preliminary remainder based codes. In ...


2
Boris Farber, Sofia Farber, Boris Lerner, Ellen Lerner: Method and equipment for automated tracking and identification of nonuniform items. John D Gugliotta, February 20, 2007: US07180014 (14 worldwide citation)

An apparatus comprising of a segmented instrument tray, precision scale, image processing system, photoelectric sensors and a Personal Computer (PC) is disclosed. Said apparatus provides an automated and accurate tracking of surgical instruments used during surgical operating procedure by counting a ...


3
Doran Oster, Gary Miller, Boris Lerner: Microphone emulation. Sabine, Donald W Marks, October 26, 2004: US06810125 (6 worldwide citation)

An emulation circuit includes a digital signal processor with a digital filter controlled by frequency response conversion parameters for converting a standard microphone signal into a signal emulating the frequency response of one of a plurality of microphones selected by a selector connected to th ...


4
Boris Lerner: Computing module for efficient FFT and FIR hardware accelerator. Analog Devices, Bingham McCutchen, August 7, 2012: US08239442 (2 worldwide citation)

A hardware accelerator operable in an FFT mode and an FIR mode. The hardware accelerator takes input data and coefficient data and performs the calculations for the selected mode. In the FFT mode, a rate-two FFT is calculated, producing four real outputs corresponding to two complex numbers. In the ...


5
Boris Lerner, Douglas Garde: Processor architectures for enhanced computational capability and low latency. Analog Devices, Bingham McCutchen, January 31, 2012: US08108653 (2 worldwide citation)

A processor includes a compute array comprising a first plurality of compute engines serially connected along a data flow path such that data flows between successive compute engines at successive times. The first plurality of compute engines includes an initial compute engine and a final compute en ...


6
Kaushal Sanghai, Boris Lerner, Michael G Perkins, John L Redford: Memory interconnect network architecture for vector processor. Analog Devices, Patent Capital Group, December 1, 2015: US09201828 (1 worldwide citation)

The present disclosure provides a memory interconnection architecture for a processor, such as a vector processor, that performs parallel operations. An example processor may include a compute array that includes processing elements; a memory that includes memory banks; and a memory interconnect net ...


7
Andrew J Higham, Boris Lerner, Kaushal Sanghai, Michael G Perkins, John L Redford, Michael S Allen: Predicate counter. ANALOG DEVICES GLOBAL, Patent Capital Group, May 17, 2016: US09342306

According to an example embodiment, a processor such as a digital signal processor (DSP), is provided with a register acting as a predicate counter. The predicate counter may include more than two useful values, and in addition to acting as a condition for executing an instruction, may also keep tra ...


8
Michael Meyer Pundsack, Boris Lerner, Gopal Gudhur Karanam, Pradip Thaker: Methods and apparatus for image processing at pixel rate. Analog Devices, Bingham McCutchen, May 14, 2013: US08441492

Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and ...


9
Boris Lerner, Pradip Thaker, Gopal Gudhur Karanam, Michael Meyer Pundsack: Methods and apparatus for image processing at pixel rate. Analog Devices, Bingham McCutchen, March 6, 2012: US08130229

Embodiments of the present invention provide for improved timing control in 2-D image processing to maintain a constant rate of memory fetches and pixel outputs even when the processing operations transition to a new line or frame of pixels. A one-to-one relationship between incoming pixel rate and ...


10
Boris Lerner: Scaling fixed-point fast Fourier transforms in radar and sonar applications. ANALOG DEVICES, Patent Capital Group, May 22, 2018: US09977116

Present disclosure describes an improved scaling mechanism for a multi-stage fixed-point FFT algorithm used to process signals received by radar or sonar systems. Proposed scaling includes scaling an output of every pair of consecutive butterfly stages of the FFT algorithm by a scaling factor equal ...