1
Bjorn Liencres, Ashok Singhal, Jeff Price, Kang S Lim: Method and apparatus for hot plugging/unplugging a sub-system to an electrically powered system. Sun Microsystems, Matthew C Rainey, July 1, 1997: US05644731 (97 worldwide citation)

The present invention provides an "alert" interface for a component which can be safely "hot-plugged/unplugged" to an "alert" interconnect of an electrically powered system. The alert interface has a mating edge which includes daughter precharge/ground connectors, a daughter (engage) waning connecto ...


2
Pradeep S Sindhu, Bjorn Liencres, Jorge Cruz Rios, Douglas B Lee, Jung Herng Chang, Jean Marc Frailong: Apparatus and method for a synchronous, high speed, packet-switched bus. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, March 16, 1993: US05195089 (54 worldwide citation)

A high speed, synchronous, packet-switched inter-chip bus apparatus and method for transferring data between multiple system buses and a cache controller. In the preferred embodiment, the bus connects a cache controller client within the external cache of a processor to a plurality of bus watcher cl ...


3
Ashok Singhal, Bjorn Liencres, Jeff Price, Frederick M Cerauskis, David Broniarczyk, Gerald Cheung, Erik Hagersten, Nalini Agarwal: Split transaction snooping bus protocol. Sun Microsystems, Flehr Hohbach Test Albritton & Herbert, June 8, 1999: US05911052 (47 worldwide citation)

A split transaction snooping bus protocol and architecture is provided for use in a system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and addres ...


4
Ashok Singhal, Bjorn Liencres, Jeff Price, Frederick M Cerauskis, David Broniarczyk, Gerald Cheung, Erik Hagersten, Nalini Agarwal: Implementing snooping on a split-transaction computer system bus. Sun Microsystems, Flehr Hohbach Test Albritton & Herbert, November 2, 1999: US05978874 (47 worldwide citation)

Snooping is implemented on a split transaction snooping bus for a computer system having one or many such buses. Circuit boards including CPU or other devices and/or distributed memory, data input/output buffers, queues including request tag queues, coherent input queues ("CIQ"), and address control ...


5
Bjorn Liencres, Douglas Lee, Pradeep S Sindhu, Tung Pham: Methods and apparatus for creating a pending write-back controller for a cache controller on a packet switched memory bus employing dual directories. Sun Microsystems, Xerox Corporation, Blakely Sokoloff Taylor & Zafman, July 18, 1995: US05434993 (46 worldwide citation)

A write-back cache control system having a pending write-back cache controller in a multiprocessor cache memory structure. The processor subsystems in the multiprocessor system are coupled together using a high-speed synchronous packet switching bus called a memory bus. Each processor subsystem has ...


6
Erik Hagersten, Ashok Singhal, Bjorn Liencres: Optimizing responses in a coherent distributed electronic system including a computer system. Sun Microsystems, Flehr Hohbach Test Albritton & Herbert, October 27, 1998: US05829033 (28 worldwide citation)

In a computer system implementing state transitions that change logically and atomically at an address packet independently of a response, the coherence domain is extended among distributed memory. As such, memory line ownership transfers upon request, and not upon requestor receipt of data. Request ...


7
Bjorn Liencres: Mechanism for implementing multiple time-outs. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, February 15, 1994: US05287362 (6 worldwide citation)

A time-out detector for a computer system to record any number of time-out events with a predetermined period. The time-out detector comprises A-counter coupled to a transmission medium for incrementing in response to an initiating event and decrementing in response to a terminating event; B-counter ...


8
Bjorn Liencres: Method and apparatus for providing a high through put cache tag controller. Sun Microsystems, Blakely Sokoloff Taylor & Zafman, March 5, 1996: US05497470 (5 worldwide citation)

A cache tag controller for a cache tag memory for receiving multiple consecutive cache tag modify operations through a system bus to update cache tags in the cache tag memory. The cache tag controller comprises memory for storing cache tags; address register coupled to the memory for specifying a ca ...


9
Pradeep Sindhu, Dennis Ferguson, Bjorn Liencres, Nalini Agarwal, Hann Hwan Ju, Raymond Marcelino Manese Lim, Rasoul Mirzazadeh Oskouy, Sreeram Veeragandham: Memory organization in a network device. Juniper Networks, Harrity & Harrity, June 24, 2014: US08761180

A router for switching data packets from a source to a destination in a network in which the router includes a distributed memory. The distributed memory includes two or more memory banks. Each memory bank is used for storing uniform portions of a data packet received from a source and linking infor ...