1
Dan Patterson, Bindi Prasad, Gurbir Singh, Peter MacWilliams, Steve Hunt, Phil G Lee: Processor-cache protocol using simple commands to implement a range of cache configurations. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 13, 2001: US06202125 (42 worldwide citation)

A computer system having a processor-cache protocol supporting multiple cache configurations is described. The computer system has a processor having a cache control circuit to control multiple cache memory circuits. The processor including its cache control circuit is coupled to a cache bus. A seco ...


2
Peter MacWilliams, Bindi Prasad, Manoji Khare, Dilip Sampath: Source synchronous interface between master and slave using a deskew latch. Intel Corporation, Blakely Sokoloff Taylor & Zafman, March 27, 2001: US06209072 (6 worldwide citation)

A source synchronous interface between a master device and slave device is described. A master device having a plurality of deskew latches is coupled to a slave device via a bus. The master device communicates commands and first timing information to the slave device via the bus. In response, the sl ...