1
Bin Yu, Judy Xilin An, Cyrus E Tabery, Haihong Wang: Method for forming multiple structures in a semiconductor device. Advanced Micro Devices, Harrity & Snyder, March 16, 2004: US06706571 (472 worldwide citation)

A method of forming multiple structures in a semiconductor device includes depositing a film over a conductive layer, etching a trench in a portion of the film and forming adjacent the sidewalls of the trench. The film may then be etched, followed by an of the conductive layer to form the structures ...


2
Bin Yu: Method of forming a double gate transistor having an epitaxial silicon/germanium channel region. Advanced Micro Devices, Foley & Lardner, November 5, 2002: US06475869 (342 worldwide citation)

A method of manufacturing an integrated circuit with a channel region containing germanium. The method can provide a double planar gate structure. The gate structure can be provided over lateral sidewalls of channel region. The semiconductor material containing germanium can increase the charge mobi ...


3
Zoran Krivokapic, Judy Xilin An, Srikanteswara Dakshina Murthy, Haihong Wang, Bin Yu: Narrow fin FinFET. Advanced Micro Devices, Harrity & Snyder, July 26, 2005: US06921963 (207 worldwide citation)

A narrow channel FinFET is described herein with a narrow channel width. A protective layer may be formed over the narrow channel, the protective layer being wider than the narrow channel.


4
Bin Yu, Eric N Paton: MOSFET having a double gate. Advanced Micro Devices, Renner Otto Boisselle & Sklar, November 11, 2003: US06646307 (192 worldwide citation)

A double gate MOSFET. The MOSFET includes a bottom gate electrode and a bottom gate dielectric disposed over the bottom gate electrode. A semiconductor body region is disposed over the bottom gate dielectric and the bottom gate electrode, and disposed between a source and a drain. A top gate electro ...


5
Matthew S Buynoski, Srikanteswara Dakshina Murthy, Cyrus E Tabery, Haihong Wang, Chih Yuh Yang, Bin Yu: Method for forming fins in a FinFET device using sacrificial carbon layer. Advanced Micro Devices, Harrity & Snyder L, November 11, 2003: US06645797 (166 worldwide citation)

A method for forming a fin in a semiconductor device that includes a substrate, an insulating layer formed on the substrate, and a conductive layer formed on the insulating layer, includes forming a carbon layer over the conductive layer and forming a mask over the carbon layer. The method further i ...


6
Bin Yu: Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology. Advanced Micro Devices, Monica H Choi, May 13, 2003: US06562665 (162 worldwide citation)

For fabricating a field effect transistor, a pillar of semiconductor material is formed, a recess is formed in the top surface of the pillar along the length of the pillar, a gate dielectric material is deposited on any exposed surface of the semiconductor material of the pillar including at the top ...


7
Srikanteswara Dakshina Murthy, Chih Yuh Yang, Bin Yu: Epitaxially grown fin for FinFET. Advanced Micro Devices, Harrity & Snyder, December 28, 2004: US06835618 (154 worldwide citation)

A method of forming a fin for a fin field effect transistor (FinFET) includes defining a trench in a layer of first material, where a width of an opening of the trench is substantially smaller than a thickness of the layer. The method further includes growing a second material in the trench to form ...


8
Matthew S Buynoski, Judy Xilin An, Haihong Wang, Bin Yu: Double spacer FinFET formation. Advanced Micro Devices, Harrity & Snyder, March 23, 2004: US06709982 (145 worldwide citation)

A method for forming a group of structures in a semiconductor device includes forming a conductive layer on a substrate, where the conductive layer includes a conductive material, and forming an oxide layer over the conductive layer. The method further includes etching at least one opening in the ox ...


9
Shibly S Ahmed, Haihong Wang, Bin Yu: Double gate semiconductor device having separate gates. Advanced Micro Devices, Harrity & Snyder, August 26, 2003: US06611029 (145 worldwide citation)

A semiconductor device may include a substrate and an insulating layer formed on the subtrate. A fin may be formed on the insulating layer and may include a number of side surfaces and a top surface. A first gate may be formed on the insulating layer proximate to one of the number of side surfaces o ...


10
Bin Yu, David Wu: Formation of high-k gate dielectric layers for MOS devices fabricated on strained lattice semiconductor substrates with minimized stress relaxation. McDermott Will & Emery, August 31, 2004: US06784101 (142 worldwide citation)

A semiconductor device is formed by providing a semiconductor substrate comprising a strained lattice semiconductor layer at an upper surface thereof and having a pre-selected amount of lattice therein, forming a thin buffer/interfacial layer of a low-k dielectric material on the upper surface of th ...



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