1
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett Jr, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple channel modules and bus systems using same. Rambus, July 20, 2004: US06765800 (46 worldwide citation)

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


2
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett Jr, Ely Tsern, Craig E Hampel, Wai Yeung Yip: Multiple channel modules and bus systems using same. Rambus, Hunton & Williams, May 24, 2005: US06898085 (37 worldwide citation)

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


3
Belgacem Haba Belgacem (Bel) Haba
Belgacem Haba, Richard E Perego, David Nguyen, Billy W Garrett Jr, Ely Tsern, Crag E Hampel, Wai Yeng Yip: Multiple channel modules and bus systems using same. Rambus, Hunton & Williams, January 30, 2007: US07170314 (2 worldwide citation)

Various module structures are disclosed which may be used to implement modules having 1 to N channels. Bus systems may be formed by the interconnection of such modules.


4
Frederick A Ware, John B Dillon, Richard M Barth, Billy W Garrett Jr, John G Atwood Jr, Michael P Farmwald: Dynamic random access memory system. Rambus, Blakely Sokoloff Taylor & Zafman, July 4, 1995: US05430676 (107 worldwide citation)

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to th ...


5
Frederick A Ware, John B Dillon, Richard M Barth, Billy W Garrett Jr, John G Atwood Jr, Michael P Farmwald: Dynamic random access memory system. Rambus, Blakely Sokoloff Taylor & Zafman, April 23, 1996: US05511024 (79 worldwide citation)

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to th ...


6
Jared L Zerbe, Bruno W Garlepp, Pak S Chau, Kevin S Donnelly, Mark A Horowitz, Stefanos Sidiropoulos, Billy W Garrett Jr, Carl W Werner: Integrating receiver with precharge circuitry. Rambus, Morgan Lewis & Bockius, June 12, 2012: US08199859 (74 worldwide citation)

An integrated circuit device includes a sense amplifier with an input to receive a present signal representing a present bit. The sense amplifier is to produce a decision regarding a logic level of the present bit. The integrated circuit device also includes a circuit to precharge the input of the s ...


7
Jared L Zerbe, Bruno W Garlepp, Pak S Chau, Kevin S Donnelly, Mark A Horowitz, Stefanos Sidiropoulos, Billy W Garrett Jr, Carl W Werner: Low latency multi-level communication interface. Rambus, Morgan Lewis & Bockius, October 17, 2006: US07124221 (27 worldwide citation)

A memory system uses multiple pulse amplitude modulation (multi-PAM) output drivers and receivers to send and receive multi-PAM sigsnals. A multi-PAM signal has more than two voltage levels, with each data interval now transmitting a “symbol” at one of the valid voltage levels. In one embodiment, a ...


8
Frederick A Ware, John B Dillon, Richard M Barth, Billy W Garrett Jr, John G Atwood Jr, Michael P Farmwald: Dynamic random access memory system. Rambus Incorporated, Blakely Sokoloff Taylor & Zafman, July 18, 1995: US05434817 (23 worldwide citation)

As interfaces to DRAMs become more advanced and higher performance, the interfaces and signal lines required to support the interface become more expensive to implement. Therefore, it is desirable to minimize the number of signal lines and maximize the bandwidth of the signal lines interfacing to th ...


9
Billy W Garrett Jr: Apparatus for creating a cursor pattern by strips related to individual scan lines. NCR Corporation, Wilbert Hawk Jr, Casimer K Salys, January 22, 1991: US04987551 (22 worldwide citation)

An architecture for generating a hardware cursor in the context of a bit mapped video display system operable from a frame buffer with non-displayed but addressable memory space. A segment of the non-displayed memory is loaded with cursor outline and pattern information. The cursor data is accessed ...


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Bruno W Garlepp, Richard M Barth, Kevin S Donnelly, Ely K Tsern, Craig E Hampel, Jeffrey D Mitchell, James A Gasbarro, Billy W Garrett Jr, Fredrick A Ware, Donald V Perino: Expandable slave device system. Rambus, Gary S Williams, Pennie & Edmonds, February 3, 2004: US06687780 (20 worldwide citation)

A bus system for use with addressable memory has a global bus of uni-directional signal lines. The global bus has a first end and a second end. A master device transmits data to and receives data from the global bus. First and second global bus terminators are coupled to the first and second ends of ...