1
Angela T Hui, Bhanwar Singh: Method of forming smaller contact size using a spacer hard mask. Advanced Micro Devices, Foley & Lardner, February 4, 2003: US06514849 (176 worldwide citation)

An exemplary method of forming contact holes includes providing a photoresist pattern over an anti-reflective coating (ARC) layer where the ARC layer is deposited over a layer of material; etching the ARC layer according to the photoresist pattern to form ARC features; forming spacers on lateral sid ...


2
Angela T Hui, Kouros Ghandehari, Bhanwar Singh: Method of forming integrated circuit features by oxidation of titanium hard mask. Advanced Micro Devices, Foley & Lardner, November 5, 2002: US06475867 (92 worldwide citation)

An exemplary method of forming integrated circuit device features by oxidization of titanium hard mask is described. This method can include providing a photoresist pattern of photoresist features over a first layer of material deposited over a second layer of material; etching the first layer of ma ...


3
Itty Matthew, Bhanwar Singh: Process margin using discrete assist features. GLOBALFOUNDRIES, Turocy & Watson, July 6, 2010: US07749662 (84 worldwide citation)

The subject invention provides a system and method for improving the process margin of a lithographic imaging system. The process margin improvement is achieved through the novel placement of discrete assist features and/or the use of forbidden pitches and specific pitch orientations. Novel geometri ...


4
Khoi A Phan, Bharath Rangarajan, Bhanwar Singh, Ramkumar Subramanian: Refractive index system monitor and control for immersion lithography. Advanced Micro Devices, Amin & Turocy, January 18, 2005: US06844206 (68 worldwide citation)

A system and/or method are disclosed for measuring and/or controlling refractive index (n) and/or lithographic constant (k) of an immersion medium utilized in connection with immersion lithography. A known grating structure is built upon a substrate. A refractive index monitoring component facilitat ...


5
Ramkumar Subramanian, Bhanwar Singh, Marina V Plat, Christopher F Lyons, Scott A Bell: RELACS process to double the frequency or pitch of small feature formation. Advanced Micro Devices, Foley & Lardner, May 7, 2002: US06383952 (61 worldwide citation)

A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by ...


6
Bhanwar Singh, Michael K Templeton, Bharath Rangarajan, Ramkumar Subramanian: Critical dimension monitoring from latent image. Advanced Micro Devices, Amin & Turocy, May 13, 2003: US06561706 (55 worldwide citation)

A system for monitoring a latent image exposed in a photo resist during semiconductor manufacture is provided. The system includes one or more light sources, each light source directing light to the latent image and/or one or more gratings exposed on one or more portions of a wafer. Light reflected ...


7
Marina V Plat, Scott A Bell, Christopher F Lyons, Ramkumar Subramanian, Bhanwar Singh: Bi-layer trim etch process to form integrated circuit gate structures. Advanced Micro Devices, Foley & Lardner, April 1, 2003: US06541360 (54 worldwide citation)

A bi-layer trim etch process to form integrated circuit gate structures can include depositing an organic underlayer over a layer of polysilicon, depositing an imaging layer over the organic underlayer, patterning the imaging layer, selectively trim etching the organic underlayer to form a pattern, ...


8
Marina V Plat, Scott A Bell, Christopher F Lyons, Ramkumar Subramanian, Bhanwar Singh: Use of silicon containing imaging layer to define sub-resolution gate structures. Advanced Micro Devices, Foley & Lardner, March 18, 2003: US06534418 (51 worldwide citation)

An exemplary method of using silicon containing imaging layers to define sub-resolution gate structures can include depositing an anti-reflective coating over a layer of polysilicon, depositing an imaging layer over the anti-reflective coating, selectively etching the anti-reflective coating to form ...


9
Sanjay K Yedur, Bhanwar Singh, Bharath Rangarajan, Ramkumar Subramanian: Topographically aligned layers and method for adjusting the relative alignment of layers and apparatus therefor. Advanced Micro Devices, Renner Otto Boisselle & Sklar, November 2, 2004: US06813574 (49 worldwide citation)

Patterned layers in an integrated circuit (IC) or other device are aligned in conjunction with the detection of the topology of the layers. The topology can be used to determine the location of a metrology mark and/or to compensate for a horizontal shift in the apparent location of the metrology mar ...


10
Fei Wang, Bhanwar Singh, James K Kai: Dual damascene process using sacrificial spin-on materials. Advanced Micro Devices, Foley & Lardner, May 2, 2000: US06057239 (44 worldwide citation)

A dual damascene process includes the steps of forming a contact hole in an oxide layer disposed above a semiconductor substrate, disposing a layer of anti-reflective coating material on top of the oxide layer and in the contact hole, and partially etching the layer of anti-reflective coating materi ...



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