1
Bernard J New: Logic structure and circuit for fast carry. Xilinx, Edel M Young, September 20, 1994: US05349250 (292 worldwide citation)

Programmable logic devices which include multiple blocks of combinatorial function generators and storage elements, and which are interconnected by a programmable interconnect structure are used, among other things for performing arithmetic functions which use logic for generating the carry function ...


2
Bernard J New, Robert Anders Johnson, Ralph Wittig, Sundararajarao Mohan: Rapidly reconfigurable FPGA having a multiple region architecture with reconfiguration caches useable as data RAM. Xilinx, E Eric Hoffman, Jeanette S Harms, July 18, 2000: US06091263 (229 worldwide citation)

A field programmable gate array (FPGA) which includes first and second arrays of configurable logic blocks, and first and second configuration cache memories coupled to the first and second arrays of configurable logic blocks, respectively. The first configuration cache memory array can either store ...


3
Bernard J New: Bit slice microprogrammable processor for signal processing applications. Advanced Micro Devices, Gary T Aka, J Ronald Richbourg, July 12, 1983: US04393468 (216 worldwide citation)

A programmable device for signal processing applications in which short loops of digital data are processed repetitively and in parallel. The device consist of five independently programmable subsystems whose functions are able to operate simultaneously. The apparatus is intended for use in a connec ...


4
Bernard J New: Dedicated function fabric for use in field programmable gate arrays. Xilinx, Bever Hoffman & Harms, February 12, 2002: US06346824 (196 worldwide citation)

A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of dedicated function blocks. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the arr ...


5
Bernard J New: Multi-chip programmable logic device having configurable logic circuitry and configuration data storage on different dice. Xilinx, T Lester Wallace, LeRoy D Maunu, Justin Liu, July 12, 2005: US06917219 (185 worldwide citation)

The circuitry of a programmable logic device (for example, an FPGA) includes a configurable logic portion and a configuration memory. The configuration memory stores configuration data that configures the configurable logic portion to realize a user-defined circuit. The configurable logic portion is ...


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Bernard J New: Field programmable gate array with dedicated computer bus interface and method for configuring both. Xilinx, E Eric Hoffman, Edel M Young, January 4, 2000: US06011407 (183 worldwide citation)

A field programmable gate array is provided which has a programmable portion and a dedicated controller-interface circuit. The programmable portion includes conventional input/output (I/O) blocks and configurable logic blocks (CLBs). The controller-interface circuit allows the FPGA to be operably co ...


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Bernard J New: Field programmable gate array with distributed gate-array functionality. Xilinx, Edel M Young, E Eric Hoffman Esq, February 23, 1999: US05874834 (165 worldwide citation)

A field programmable gate array (FPGA) having a plurality of configurable logic blocks (CLBs). Each of the CLBs includes programmable interconnect resources, a field programmable configurable logic element (CLE) circuit and a corresponding non-field programmable gate array. The programmable intercon ...


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Bernard J New, Richard A Carberry: Programmable logic device having configurable logic blocks with user-accessible input multiplexers. Xilinx, Arthur J Behiel, Lois D Cartier, September 18, 2001: US06292019 (142 worldwide citation)

A programmable logic device (PLD) includes at least one function generator capable of implementing any arbitrarily defined Boolean function of input signals. The PLD includes a dynamically controlled multiplexer (MUX) on each function-generator input terminal. The inputs of each MUX can be routed to ...


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Bernard J New, Steven P Young: Method and apparatus for incorporating a multiplier into an FPGA. Xilinx, Edel M Young, March 26, 2002: US06362650 (142 worldwide citation)

One or more columns of multi-function tiles are positioned between CLB tiles of the FPGA array. Each multi-function tile includes multiple function elements that share routing resources. In one embodiment, a multi-function tile includes a configurable, dual-ported RAM and a multiplier that share rou ...


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Bernard J New: Multiplier fabric for use in field programmable gate arrays. Xilinx, E Eric Hoffman, Lois D Cartier, Bever Hoffman & Harms, November 28, 2000: US06154049 (134 worldwide citation)

A programmable logic device, such as a field programmable gate array (FPGA) which includes an array of configurable logic elements (CLEs) and a corresponding array of multiplier tiles. The CLEs can be operated as conventional configurable logic elements, completely disconnected from the array of mul ...