1
Richard J Eickemeyer, Stamatis Vassiliadis, Bartholomew Blaner: In-memory preprocessor for compounding a sequence of instructions for parallel computer system execution. International Business Machines Corporation, Lynn L Augspurger, Terrance A Meador, October 11, 1994: US05355460 (91 worldwide citation)

A digital computer system capable of processing two or more computer instructions in parallel and having a main memory unit for storing information blocks including the computer instructions includes an instruction compounding unit for analyzing the instructions and adding to each instruction a tag ...


2
Bartholomew Blaner, Stamatis Vassiliadis: Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism. International Business Machines Corporation, Lynn L Augspurger, May 25, 1993: US05214763 (83 worldwide citation)

A digital computer system capable of processing two or more computer instructions in parallel and having a cache storage unit for temporarily storing machine-level computer instructions in their journey from a higher-level storage unit of the computer system to the functional units which process the ...


3
Bartholomew Blaner, Thomas L Jeremiah, Stamatis Vassiliadis, Phillip G Williams: Pipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unit. International Business Machines Corporation, Lynn L Augspurger, February 15, 1994: US05287467 (82 worldwide citation)

The parallelism of a multi-pipelined digital computer is enhanced by detection of branch instructions from the execution pipelines and concurrent processing of up to two of the detected instructions in parallel with the operations of the execution pipelines. Certain branch instructions, when detecte ...


4
Bartholomew Blaner, Agnes Y Ngai: Apparatus and method for implementing precise interrupts on a pipelined processor with multiple functional units with separate address translation interrupt means. International Business Machines Corporation, Karl F Milde Jr, March 26, 1991: US05003462 (80 worldwide citation)

An apparatus and method are disclosed for implementing the system architectural requirement of precise interrupt reporting in a pipelined processor with multiple functional units. Since the expense of an interrupt pipeline is warranted only for those interrupts that occur frequently--specifically, t ...


5
James E Phillips, Bartholomew Blaner, Stamatis Vassiliadis: Multi-function permutation switch for rotating and manipulating an order of bits of an input data byte in either cyclic or non-cyclic mode. International Business Machines Corporation, Lynn L Augspurger, Laurence J Marhoefer, November 28, 1995: US05471628 (78 worldwide citation)

In a digital computer system both rotation of bits in a data byte and rotation in combination with additional manipulation, a multifunction permutation switch, in a cyclic mode of operation, connects the input bit lines to the output bit lines so that the sequence of input bits are maintained on the ...


6
James E Phillips, Bartholomew Blaner, Stamatis Vassiliadis: Status predictor for combined shifter-rotate/merge unit. International Business Machines Corporation, Lynn L Augspurger, Richard L Aitken, December 31, 1996: US05590348 (66 worldwide citation)

Generation of functional status followed by the use of the status to control the sequencing of microinstructions is a well known critical path in processor designs. The delay associated with the path is exacerbated in superscalar machines by the additional statuses that are produced by multiple func ...


7
Bartholomew Blaner, Larry D Larsen: Multiple condition code branching system in a multi-processor environment. International Business Machines Corporation, Steven B Phillips, George E Clark, August 19, 1997: US05659722 (64 worldwide citation)

A data processing system includes a number of processing elements wherein each of the processing elements generates one or more condition signals, one or more memory elements associated with the processing elements for storing instructions and data associated with the processing elements, at least o ...


8
Stamatis Vassiliadis, James E Phillips, Bartholomew Blaner: Data dependency collapsing hardware apparatus. International Business Machines Corporation, Baker Maxham Jester & Meador, September 24, 1991: US05051940 (64 worldwide citation)

A multi-function ALU (arithmetic/logic unit) for use in digital data processing facilitates the execution of instructions in parallel, thereby enhancing processor performance. The proposed apparatus reduces the instruction execution latency that results from data dependency hazards in a pipelined ma ...


9
Stamatis Vassiliadis, Bartholomew Blaner, Thomas L Jeremiah: System for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tag. International Business Machines Corporation, Lynn L Augspurger, April 12, 1994: US05303356 (51 worldwide citation)

An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execu ...


10
Stamatis Vassiliadis, Bartholomew Blaner, Thomas L Jeremiah: System for executing scalar instructions in parallel based on control bits appended by compounding decoder. International Business Machines Corporation, Lynn L Augspurger, Richard L Aitken, April 2, 1996: US05504932 (41 worldwide citation)

An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execu ...



Click the thumbnails below to visualize the patent trend.