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Haskell Jacob B, Sander Craig S, Avanzino Steven C, Gupta Subhash Nmi: Improved method of planarization of topologies in integrated circuit structures.. Advanced Micro Devices, November 15, 1989: EP0341898-A2 (19 worldwide citation)

A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height highe ...


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Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven, LAM Christine S, May 26, 2006: WO/2006/055482 (12 worldwide citation)

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


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Avanzino Steven C, Haskell Jacob D, Gupta Subhash: Improved method of planarization of topologies in integrated circuit structures.. Advanced Micro Devices, January 9, 1991: EP0407047-A2 (10 worldwide citation)

A method is disclosed for making a highly planarized integrated circuit structure having deposited oxide portions planarized to the level of adjacent portions of the integrated circuit structure which comprises: depositing, over an integrated circuit structure having first portions at a height highe ...


4
Haskell Jacob D, Avanzino Steven C, Swanimathan Balaji Nmn: Doping process.. Advanced Micro Devices, August 14, 1991: EP0441482-A1 (4 worldwide citation)

A process is provided for doping both sidewalls (26, 28) of isolation trenches (24, 26, 28) and connector regions (46, 48) between sources (58) and gate areas and between drains (60) and gate areas in silicon CMOS devices. Appropriately doped glasses (16, 18, 30) formed on the silicon substrate (14) ...


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Sultan Pervaiz, Avanzino Steven C: Void free oxide fill for interconnect spaces.. Advanced Micro Devices, February 23, 1994: EP0583866-A1 (1 worldwide citation)

An improved interconnect space filling process which provides voidless space filling for aspect ratio


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Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, August 1, 2007: GB2434694-A

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


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Avanzino Steven, Sokolik Igor, Pangrle Suzette K, Tripsas Nicholas H, Shields Jeffrey A: Protection of active layers of memory cells during processing of other elements. Spansion, chengwei wangjin yang, October 17, 2007: CN200580038928

A method of fabricating an electronic structure by providing a conductive layer (102), providing a dielectric layer (100) over the conductive layer (102), providing first and second openings (104, 106) through the dielectric layer (100), providing first and second conductive bodies (108, 110) in the ...


10
Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, chengwei wangjin yang, October 17, 2007: CN200580039025

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...