1
Hirotsugu Kojima, Avadhani Shridhar: Method and apparatus for reducing the power consumption in a programmable digital signal processor. Hitachi America, Flehr Hohbach Test Albritton & Herbert, March 9, 1999: US05880981 (67 worldwide citation)

The present invention contemplates an improved multiplier circuit and method for reducing power consumption by reducing the number of transitions to the input of the multiplier. Each input to the multiplier is fixed for as long as possible by reordering the sequence of the multiplications to take ad ...


2
Avadhani Shridhar, John Simons: Embedded debug commands in a source file. Hitachi America, Flehr Hohbach Test Albritton & Herbert, September 29, 1998: US05815714 (37 worldwide citation)

A method and apparatus for re-generating debug commands is provided comprising a source program having embedded debug commands in a first distinguishable field, and an assembler. The assembler operates on the source code extracting the embedded debug commands and associated address information from ...


3
Avadhani Shridhar, Kenichi Nitta: Repeat-bit based, compact system and method for implementing zero-overhead loops. Hitachi America, Douglas J Flehr Hohbach Test Albritton & Herbert Crisman, March 10, 1998: US05727194 (34 worldwide citation)

A repeat-bit based system and method for executing zero overhead loops, or repeat loops, in an information processing chip that does not require a repeat end register or a dedicated comparator. Executing repeat loops requires a processor to iterate N times a code fragment of loop instructions. All s ...


4
Avadhani Shridhar, T R Ramesh, Raminder S Bajwa, Masoud Eskandari, Firooz Massoudi, Omprakash S Sarmaru, Behrooz Rezvani: Method and apparatus for synchronizing a packet based modem supporting multiple X-DSL protocols. Ikanos Communications, IP Creators, Charles C Cary, January 11, 2005: US06842429 (26 worldwide citation)

The current invention provides a digital signal processor which supports multiple X-DSL protocols and a multiplicity of channels on a single chip. Each channel is packetized and each packet includes control information for controlling the performance of the components/modules on the transmit and rec ...


5
Avadhani Shridhar, Douglas J Gorny: Modulo arithmetic addressing circuit. Hitachi America, Flehr Hohbach Test Albritton & Herbert, January 10, 1995: US05381360 (18 worldwide citation)

A modulo addition circuit generates a sequence of values within a specified range having a lower bound value and an upper bound value. The modulo addition circuit generates a first value by adding a displacement value to a previously defined starting value, and generates a second value by adding to ...


6
Behrooz Rezvani, Avadhani Shridhar, Raminder S Bajwa, Tiruvur R Ramesh, Masoud Eskandari, Firooz Massoudi, Sam Heidari, Omprakash S Sarmaru, Sridhar Begur: Method and apparatus for a X-DSL communication processor. Velocity Communication, IP Creators, Charles C Cary, September 6, 2005: US06940807 (17 worldwide citation)

The current invention provides a DSP which accommodates multiple current X-DSL protocols and is further configurable to support future protocols. The DSP is implemented with shared and dedicated hardware components on both the transmit and receive paths. The DSP implements both the discrete Fourier ...


7
Avadhani Shridhar, Arindam Saha: System and method for performing a fast fourier transform using a matrix-vector multiply instruction. Hitachi America, Flehr Hohbach Test Albritton & Herbert, April 2, 2002: US06366937 (16 worldwide citation)

A system and method that implement a butterfly operation for a fast fourier transform operation in a processor using a matrix-vector-multiply instruction. A first set of inputs to the butterfly operation are defined as r1+j i1 and r2+j i2, and a twiddle factor Wn is defined as Wn=e


8
Sam Heidari, Behrooz Rezvani, Raminder S Bajwa, Jacky Chow, Avadhani Shridhar, Dale Smith, John Gevargiz, Saman Behtash: Method and apparatus for a variable bandwidth multi-protocol X-DSL transceiver. Ikanos Communication, IP Creators, Charles C Cary, January 1, 2008: US07315571 (14 worldwide citation)

A transceiver for communicating a multi-tone modulated communication channel on a subscriber line. The transceiver includes: a digital signal processor (DSP) with a Fourier transform module and an analog front end (AFE). The DSP determines an available range of frequencies on the subscriber line and ...


9
Avadhani Shridhar, Behrooz Rezvani, Sushil Agarwal, Alfred Mui, Masoud Eskandari: Method and apparatus for dynamic multi-line bonding in communication systems. Ikanos Communication, IP Creators, Charles C Cary, July 29, 2008: US07406042 (9 worldwide citation)

A bundler, un-bundler and sequencer for use in controlling and driving opposing sets of logical or physical modems to drive multiple-subscriber lines with multiple communication channels. The sequencer determines subscriber requirements such as maximum and minimum bandwidth and quality of service. T ...


10
Avadhani Shridhar, Abhijit Shah: Method and apparatus for an interleaver. Ikanos Communications, IP Creators, Charles C Cary, August 18, 2009: US07577881 (9 worldwide citation)

A modem configured to couple to a communication medium for establishing a communication channel thereon. The modem includes an interleaver component configurable as to interleaver parameters ‘I, D’ corresponding to block length and depth respectively. An interleaver memory buffers the communication ...



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