1
Darrell M Erb, Asim A Selcuk: Shallow groove capacitor fabrication method. Advanced Micro Devices, Eugene H Valet, Patrick T King, March 17, 1987: US04650544 (48 worldwide citation)

A shallow capacitor cell is formed by using conventional integrated circuit processes to build a substrate mask having sublithographic dimensions. Multiple grooves, or trenches, are etched into the substrate using this mask. The capacitor dielectric layer and plate are then formed in the grooves.


2
Asim A Selcuk, Pau ling Chen, Darrell M Erb: High density dram trench capacitor isolation employing double epitaxial layers. Advanced Micro Devices, Ashen Golant Martin & Seldon, February 27, 1990: US04905065 (22 worldwide citation)

A new double-epitaxial structure for isolating deep (>5 .mu.m) trench capacitors (10, 10') with 1 .mu.m or less spacing (S) is disclosed. The structure comprises a thin, lightly doped upper epitaxial layer (16) on top of a thicker and more heavily doped bottom epitaxial layer (14). The low resistivi ...


3
Asim A Selcuk: Static random access memory cell having buried sidewall transistors, buried bit lines, and buried vdd and vss nodes. Advanced Micro Devices, Foley & Lardner, November 9, 1999: US05981995 (15 worldwide citation)

A static random access memory (SRAM) cell has a decreased cell size and utilizes transistors disposed in a number of trenches. Four trenches generally contain six transistors associated with the memory cell. The transistors are provided as sidewall transistors which are coupled to buried bit lines, ...


4
Richard K Klein, Asim A Selcuk, Nicholas J Kepler, Craig S Sander, Christopher A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Forming local interconnects in integrated circuits. Advanced Micro Devices, Foley & Lardner, April 18, 2000: US06051881 (13 worldwide citation)

A method and the resulting device to permit the formation of minimal insulating space between polysilicon gates by forming an insulating layer over the polysilicon gates and protecting selected ones of the gates and the insulating layer with an etch barrier so that the opening for local interconnect ...


5
Asim A Selcuk, Raymond T Lee: Method of making static random access memory cell having a trench field plate for increased capacitance. Advanced Micro Devices, Foley & Lardner, March 9, 1999: US05879980 (13 worldwide citation)

A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure disposed in a trench. The capacitive structure includes an oxide liner disposed underneath a polysilicon or tungsten plug. The polysilicon plugs are each isolated from the ...


6
Stephen C Horne, Richard K Klein, Asim A Selcuk, Nicholas John Kepler, Christopher A Spence, Raymond T Lee, John C Holst: Memory device using a reduced word line voltage during read operations and a method of accessing such a memory device. Advanced Micro Devices, Foley & Lardner, August 18, 1998: US05796651 (11 worldwide citation)

A memory device uses a reduced word line voltage during READ operations. The memory device includes a memory cell and a pass transistor for accessing the cell. The cell includes a storage node coupled to a pull-down transistor having substantially the same conductivity as the pass transistor. A driv ...


7
Asim A Selcuk: Static random access memory cell having buried sidewall capacitors between storage nodes. Advanced Micro Devices, Foley & Lardner, October 10, 2000: US06130470 (9 worldwide citation)

A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure disposed in a trench. The capacitive structure includes an oxide liner disposed underneath two polysilicon plates. The polysilicon plates are each connected to drains of l ...


8
Asim A Selcuk: Static random access memory cell utilizing enhancement mode N-channel transistors as load elements. Advanced Micro Devices, Foley & Lardner, August 11, 1998: US05793671 (8 worldwide citation)

An SRAM cell for use in a microprocessor includes enhancement mode load transistors. A control or bias circuit is coupled to the gates and drains of the load transistors to appropriately bias the load transistors. The bias circuit responds to feedback from a dummy cell to appropriately bias the load ...


9
Nicholas John Kepler, Asim A Selcuk, Richard K Klein, Craig S Sander, John C Holst, Christopher A Spence, Raymond T Lee, Stephen C Horne: Memory cell having increased capacitance via a local interconnect to gate capacitor and a method for making such a cell. Advanced Micro Devices, Foley & Lardner, December 1, 1998: US05844836 (7 worldwide citation)

A static random access memory (SRAM) cell having increased cell capacitance at the storage nodes utilizes a capacitive structure. The capacitive structure includes a dielectric material between polysilicon conductive lines and tungsten local interconnects. The polysilicon plates are each connected t ...


10
Craig S Sander, Rich K Klein, Asim A Selcuk, Nicholas J Kepler, Christoper A Spence, Raymond T Lee, John C Holst, Stephen C Horne: Minimizing transistor size in integrated circuits. Advanced Micro Devices, Foley & Lardner, April 11, 2006: US07026691 (4 worldwide citation)

A method for fabricating a field effect transistor (FET) in and on a semiconductor substrate with local interconnects to permit the formation of minimal space between gate and the local interconnects by fabricating the source and drain of the FET and the local interconnects prior to forming the gate ...