1
Asher Hazanchuk, Benjamin Esposito: Variable fixed multipliers using memory blocks. Altera Corporation, Morrison & Foerster, September 13, 2005: US06943579 (104 worldwide citation)

A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation resu ...


2
Asher Hazanchuk, Aleksander M Movshovich: Technique for accessing and refreshing memory locations within electronic storage devices which need to be refreshed with minimum power consumption. Zilog, Majestic Parsons Siebert & Hsue, July 16, 1996: US05537564 (15 worldwide citation)

A technique for accessing and refreshing memory locations within a plurality of electronic storage devices which need to be refreshed is disclosed. The technique allows for the accessing of memory locations within the plurality of devices row-by-row such that all memory locations having the same row ...


3
Asher Hazanchuk: Programmable logic device with soft multiplier. Altera Corporation, Morrison & Foerster, May 3, 2005: US06888372 (8 worldwide citation)

A programmable logic device is provided which includes a multi-port RAM block with a first port including first address registers and first data registers and with a second port including second address registers and a second data registers. At least one look-up table is stored in the RAM block. Fir ...


4
Asher Hazanchuk, Benjamin Esposito: Variable fixed multipliers using memory blocks. Altera Corporation, Martine Penilla & Gencarella, April 8, 2008: US07356554 (6 worldwide citation)

A programmable logic device includes at least one RAM block generating a first multi-bit calculation result which may, but does not necessarily, involve a multiplication of two operands. A shift operation is driven by a second multi-bit calculation result shifts the second multi-bit calculation resu ...


5
Asher Hazanchuk, Ian Ing, Satwant Singh: Method and systems to align outputs signals of an analog-to-digital converter. Lattice Semiconductor Corporation, MacPherson Kwok Chen & Heid, Greg J Michelson, March 25, 2008: US07348914 (4 worldwide citation)

Systems and methods are disclosed herein to provide improved alignment of output signals of an analog-to-digital converter (ADC). For example, in accordance with an embodiment of the present invention, a method of aligning digital signals appearing on signal paths of a parallel data bus includes sam ...


6
Asher Hazanchuk, Benjamin Esposito: Method and apparatus for implementing a multiplier utilizing digital signal processor block memory extension. Altera Corporation, L Cho, July 26, 2011: US07987222 (1 worldwide citation)

A method for performing multiplication on a field programmable gate array includes generating a product by multiplying a first plurality of bits from a first number and a first plurality of bits from a second number. A stored value designated as a product of a second plurality of bits from the first ...


7
Chang Choo, Asher Hazanchuk: Apparatus and method for implementing efficient arithmetic circuits in programmable logic devices. Altera Corporation, Morgan Lewis & Bockius, October 17, 2006: US07124161 (1 worldwide citation)

Efficient implementation of arithmetic circuits in programmable logic devices by using Look-Up Tables (LUTs) to store pre-calculated values. A table look-up operation is performed in place of complex arithmetic operations. In this way, at the expense of a few LUTs, many logic elements can be saved. ...


8
Asher Hazanchuk, Ian Ing, Satwant Singh: Digital signal processing block architecture for programmable logic device. Lattice Semiconductor Corporation, June 11, 2013: US08463832 (1 worldwide citation)

Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signal ...


9
Asher Hazanchuk: Programmable logic device data rate booster for digital signal processing. Lattice Semiconductor Corporation, March 10, 2015: US08977885

A programmable logic device is provided that includes: a programmable interconnect adapted to route input signals through the device at a system clock rate; and a digital signal processor (DSP) block coupled to the interconnect, the DSP block including: a plurality of input ports; an input register ...


10
Asher Hazanchuk: Parallel samples, parallel coefficients, time division multiplexing correlator architecture. Altera Corporation, L Cho, March 30, 2010: US07688919

A method for managing a code sequence is disclosed. First intermediate correlation values for a first plurality of sample sequences are determined during a first clock cycle. Second intermediate correlation values for the first plurality of sample sequences are determined during a second clock cycle ...