1
Arroyo Ronald Xavier, Hanna James Thomas: Clock circuit for a data processor.. Ibm, October 21, 1987: EP0242010-A1 (52 worldwide citation)

A clock circuit for supplying a clock signal 62 to a data processor 10 is arranged to supply the clock signal at one of a range of frequencies, under the control of the data processor. The processor can instruct the circuit to supply the clock signal at a maximum frequency to provide maximum data pr ...


2
Arroyo Ronald Xavier, Day Michael Norman, Edrington Jimmie Darius, Hanna James Thomas, Hunt Gary Thomas, Pancoast Steven Taylor: Information processing system.. Ibm, July 29, 1987: EP0230351-A2 (42 worldwide citation)

A method and apparatus for powering down a computer system while saving the state of the system at power down is disclosed. The system maintains the capability to suspend the execution of an application program operating on the system at any point and resuming execution of the application program at ...


3
Arroyo Ronald Xavier, Burky William E, Joyner Jody Bern: Method and system for efficiently handling memory operations in a data processing system. International Business Machines Corporation, January 1, 2002: TW470881 (2 worldwide citation)

A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory co ...


4
Arroyo Ronald Xavier, Pham Khuong Huu: Multi processor system. Ibm, June 17, 1998: EP0848318-A2 (1 worldwide citation)

A method and apparatus of allowing processors of different speeds to be used in a multi-processor system are disclosed. The method and apparatus comprise a programmable array logic (PAL) or field programmable gate array (FPGA) that detects each of the processors maximum speed and selects a speed com ...


5
Muhich John Stephen, Wright Charles Gordon, Arroyo Ronald Xavier, Merkel Lawrence Joseph: Method to improve bus latency and to allow burst transfers of unknown length. Ibm, June 26, 1996: EP0718772-A1 (1 worldwide citation)

A mechanism is provided in a microprocessor bus interface to eliminate the turnabout in those cases where the same slave is involved in consecutive read data bus tenures or where the same master and slave are involved in consecutive write data bus tenures. A new optional signal is added to the bus i ...


6
Arroyo Ronald Xavier, Burky William E, Joyner Jody B: Methode et systeme dexecution efficace doperations dans un systeme de traitement de donnees, Method and system for efficiently handling operations in a data processing system. International Business Machines Corporation, International Business Machines Corporation, WANG PETER, June 2, 2009: CA2289402

A shared memory multiprocessor (SMP) data processing system includes a store buffer implemented in a memory controller for temporarily storing recently accessed memory data within the data processing system. The memory controller includes control logic for maintaining coherency between the memory co ...


7
Anderson Gary Dean, Arroyo Ronald Xavier, Frey Bradly George, Guthrie Guy Lynn: I/o page kill definition for improved dma and l1/l2 cache performance. International Business Machines Corporation, October 1, 2001: TW457433

A special ""I/O"" page, is defined as having a large size (e.g., 4K bytes), but with distinctive cache line characteristics. For DMA reads, the first cache line in the I/O page may be accessed, by a PCI Host Bridge, as a cacheable read and all other lines are non-cacheable access (DMA Read with no i ...


8
Muhich John S, Arroyo Ronald Xavier, Wright Charles Gordon, Merkel Lawrence Joseph: Method for eliminating bus turn-around cycle, and computer system. Internatl Business Mach Corp &Lt IBM&Gt, October 11, 1996: JP1996-263430

PROBLEM TO BE SOLVED: To perform the allocation of a bus at a high speed in the case of being related to read data bus stationed time when the same slave is continued or write data bus stationed time when the same master and slave are continued. SOLUTION: New selectable signals are added to a bus in ...


9
Gary Dean Anderson, Arroyo Ronald Xavier, Bradley George Frey, Guy Lynn Guthrie: Method and device for improving directory memory access and cache performance. Internatl Business Mach Corp &Lt IBM&Gt, November 2, 2000: JP2000-305842

PROBLEM TO BE SOLVED: To provide a method and a device for improving the speed and efficiency of a direct memory access device. SOLUTION: A specific I/O page has a large size and is defined so as to have a distinguishable cache line characteristic. In the case of DMA reading, a 1st cache line in the ...


10
Gary Dean Anderson, Arroyo Ronald Xavier, Bradley George Frey, Guy Lynn Guthrie: Method and device for improving directory memory access and l1/l2 cache performance, and computer program product. International Business Machines Corporation, January 26, 2001: KR1020000011581

PURPOSE: A method and a device are provided to improve the speed and efficiency of a direct memory access device and to reduce a number of system bus instruction necessary for changing buffer state of L1/L2 cache. CONSTITUTION: A specific I/O page has a large size and is defined so as to have a dist ...