1
Balmukund Sharma, Mossaddeq Mahmood, Arnold Ginetti: Apparatus and method for synthesizing integrated circuits using parameterized HDL modules. VLSI Technology, William S Galliani, Flehr Hohbach Test Albritton & Herbert, November 24, 1998: US05841663 (282 worldwide citation)

A method and apparatus for designing circuits uses parameterized Hardware Description Language (HDL) modules stored in a library. A datapath synthesizer accesses the library and assigns values to parameters to form specific implementations of the parameterized HDL modules. The specific implementatio ...


2
Arnold Ginetti, Mossaddeq Mahmood, Balmukund Sharma: Apparatus and method for improving the timing performance of a circuit. VLSI Technology, Flehr Hohbach Test Albritton & Herbert, June 20, 1995: US05426591 (81 worldwide citation)

A computer aided design system and method for automatically modifying a specified Hardware Description Language (HDL) characterization of a circuit to reduce signal delays on critical paths of the circuit is described. The specified circuit is analyzed with a logic synthesizer including a novel cell ...


3
Arnold Ginetti: Automated circuit design system and method for reducing critical path delay times. VLSI Technology, Flehr Hohbach Test Albritton & Herbert, March 7, 1995: US05396435 (76 worldwide citation)

A computer aided design system automatically modifies a specified circuit netlist to reduce signal delays on critical signal paths. A critical signal path that does not meet specified timing constraints is identified by computing signal slack values for each node, where negative slack values indicat ...


4
Arnold Ginetti: Method and apparatus for physical budgeting during RTL floorplanning. Cadence Design Systems, John W Carpenter, Reed Smith Crosby Heafey, September 16, 2003: US06622291 (69 worldwide citation)

A feasible floorplan of a circuit is determined and budgeted in the early phases of circuit design. The process of determining the floorplan and budget includes estimating RTL complexity, physical partitioning, block placement, block i/o placement and top level global routing, and verifying feasibil ...


5
Mossaddeq Mahmood, Balmukund K Sharma, Arnold Ginetti, Francois Silve: Method for improving the operation of a circuit through iterative substitutions and performance analyses of datapath cells. VLSI Technology, William S Galliani, Flehr Hohbach Test Albritton & Herbert, June 9, 1998: US05764525 (62 worldwide citation)

A method of designing a circuit is described. A netlist for a circuit is generated. An analysis of the netlist is then executed to generate a set of cell instance performance values that characterize the performance of multiple gate instance-level components of the circuit in view of a selected para ...


6
Mossaddeq Mahmood, Mandalagiri Chandrasekhar, Arnold Ginetti, Balmukund K Sharma: Method and apparatus for characterizing timing behavior of datapaths for integrated circuit design and fabrication. VLSI Technology, Hickman Beyer & Weaver, March 10, 1998: US05726902 (52 worldwide citation)

A method and apparatus for characterizing the timing behavior of datapath in integrated circuit design and fabrication. A set of circuit specifications for an integrated circuit are developed and described in a hardware description language (HDL) description. A datapath library including datapath ce ...


7
Arnold Ginetti, Thomas J Schaefer, Robert D Shur, Christopher H Kingsley: Automated optimization of hierarchical netlists. VLSI Technology, Flehr Hohbach Test Albritton & Herbert, September 21, 1999: US05956257 (41 worldwide citation)

A method of automatically optimizing a hierarchical netlist of integrated circuit cells comprising at least one upper-level cell containing a multiplicity of subsidiary cells of lower hierachical level includes receiving data defining said netlist and timing constraints for it, and establishing abst ...


8
Arnold Ginetti, Fran cedilla ois Silve, Jean Michel Fernandez: Method and a system for fixing hold time violations in hierarchical designs. VLSI Technology, Burns Doane Swecker & Mathis, April 20, 1999: US05896299 (31 worldwide citation)

The invention relates to a computer implemented process for fixing hold time violations in hierarchical designs of electronic circuits. The process comprises the steps of:


9
Kenneth Ferguson, Randy Bishop, Arnold Ginetti, Gilles Lamant: Systems and methods of editing cells of an electronic circuit design. Cadence Design Systems, Kilpatrick Townsend & Stockton, October 25, 2011: US08046730 (31 worldwide citation)

Systems and methods to enable a user to edit subMaster content of selected instances of an electronic layout design, including editing the contents of selected instances of an existing subMaster of an EDA design, generating a new subMaster to incorporate the modified contents of the selected instanc ...


10
Arnold Ginetti, Gerrard Tarroux, Francois Silve, Jean Michel Fernandes, Philippe Troin, Jean Charles Giomi: Method and system for floorplanning a circuit design at a high level of abstraction. VLSI Technology, Burns Doane Swecker & Mathis L, January 2, 2001: US06170080 (29 worldwide citation)

A method and a system implement a circuit design in an integrated chip. A floorplan of the circuit design is arranged at a high level of abstraction. The design is synthesized based on the floorplan, and the synthesized design is laid out physically on the integrated circuit.