1
Arnold Blum, Manfred Perske, Manfred Schmidt: Cascade compressor. International Business Machines Corporation, Francis J Thornton, January 7, 1992: US05078581 (79 worldwide citation)

The compressor cascade comprises a plurality of tandem-connected membrane pumps, each of the pumps having a plurality of stroke chambers whose volumes decrease in the direction of the fluid flow through the pumps. Each chamber has several parallel-connected input/output channels for interconnecting ...


2
Arnold Blum, Gottfried Goldrian, Wolfgang Kumpf: Routing control information via a bus selectively controls whether data should be routed through a switch or a bus according to number of destination processors. International Business Machines Corporation, Arthur J Samodovitz, November 14, 1995: US05467452 (59 worldwide citation)

The invention concerns the transfer of data information in a multiprocessor computer system. If data information has to be transferred between two processor units then the associated control information is made available on a connection bus and the data information is transferred afterwards via a sw ...


3
Arnold Blum, Horst VON DER Heyden, Fritz Irro, Stephan Richter, Helmut Schaal, Hermann Schulze Schoelling: Instruction execution modification mechanism for time slice controlled data processors. International Business Machines Corporation, Cyril A Krenzer, Richard E Bee, August 22, 1978: US04109311 (42 worldwide citation)

An instruction execution modification mechanism is described for a digital data processor wherein multiple programs or tasks are performed in a concurrent manner by means of a time slice mechanism which causes the instructions from the different programs to be executed in an interleaved manner. Inst ...


4
Arnold Blum: Method and apparatus for bus arbitration in a data processing system. International Business Machines Corporation, Douglas R McKechnie, May 26, 1987: US04669079 (37 worldwide citation)

In a bus-oriented computer system, the decision as to which unit is to receive the bus takes account of the current status of the bus system and the respective operation to be performed on the bus. For that purpose, status information of the connected units, the bus command to be executed and the ad ...


5
Arnold Blum: Testing and diagnostic device for digital computers. International Business Machines Corporation, John H Bouchard, Saul S Seinberg, November 4, 1986: US04621363 (36 worldwide citation)

The detailed testing of processors, manufactured according to very large scale integration principles, which also extends to secondary functions of operations, such as the setting or non-setting of particular state indicators, necessitates the transfer of large quantities of test data between the pr ...


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Arnold Blum: Decentralized generation of synchronized clock control signals having dynamically selectable periods. International Business Machines Corporation, Saul A Seinberg, December 6, 1983: US04419739 (28 worldwide citation)

In a microprogrammed processor consisting of several circuitized chips, which are to be synchronously operated, each chip is provided with its own local clock generator or T-ring for deriving therefrom timing signals required during the subphases of micro instruction execution. A master clock connec ...


8
Arnold Blum: Built-in parallel testing circuit for use in a processor. International Business Machines, Mark Levy, August 18, 1987: US04688222 (23 worldwide citation)

The invention concerns arrangements and methods for error testing and diagnosing processors (e.g., 9; FIG. 2), whose logic subsystems (20) are interconnected by storage elements (23, 24) which in the error test and diagnostic mode are connected in the form of shift register means for the shift clock ...


9
Arnold Blum, Fritz Irro, Guenther Sonntag: Highly available computer system. International Business Machines Corporation, Roy R Schlemmer, May 25, 1976: US03959638 (21 worldwide citation)

For increasing the availability of a modular computer, a control unit and switches are provided, the latter being connected in between the control storages and the remaining identical hardware of the processor. In the case of a hardware error of one processor, its control storage is switched for a s ...


10
Arnold Blum: Shift register latch circuit means for check and test purposes and contained in LSI circuitry conforming to level sensitive scan design (LSSD) rules and techniques. International Business Machines Corporation, Wesley DeBruin, January 24, 1984: US04428060 (18 worldwide citation)

LSI circuitry conforming to LSSD rules and techniques usually requires at least a small portion of circuitry used only for check and test purposes. The disclosed circuitry meets the LSSD design rules and techniques and considerably reduces the test circuit overhead. The disclosure modifies the known ...