1
Harish Kumar, Aravindh Baktha, Mike D Upton, KS Venkatraman, Herbert H Hum, Zhongying Zhang: Method and apparatus for handling locks. Intel Corporation, Kerry D Tweet, July 26, 2005: US06922745 (19 worldwide citation)

A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a ...


2
Per Hammarlund, Aravindh Baktha, Michael D Upton, Venkat K S Venkatraman: Use of a context identifier in a cache memory. Intel Corporation, Blakely Sokoloff Taylor & Zafman, August 1, 2006: US07085889 (2 worldwide citation)

A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may b ...


3
Per H Hammarlund, Stephan Jourdan, Sebastien Hily, Aravindh Baktha, Hermann Gartler: Apparatus and method for store address for store address prefetch and line locking. Intel Corporation, Kenyon & Kenyon, October 31, 2006: US07130965 (1 worldwide citation)

Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffe ...


4
Guillermo J Rozas, Alexander Klaiber, James van Zoeren, Paul Serris, Brad Hoyt, Sridharan Ramakrishnan, Hens Vanderschoot, Ross Segelken, Darrell D Boggs, Magnus Ekman, Aravindh Baktha, David Dunn: Queued instruction re-dispatch after runahead. NVIDIA CORPORATION, November 21, 2017: US09823931

Various embodiments of microprocessors and methods of operating a microprocessor during runahead operation are disclosed herein. One example method of operating a microprocessor includes identifying a runahead-triggering event associated with a runahead-triggering instruction and, responsive to iden ...


5
KS Venkatraman, Aravindh Baktha: Placing front instruction in replay loop to front to place side instruction into execution stream upon determination of criticality. Intel Corporation, Kerry D Tweet, June 27, 2006: US07069424

A method and apparatus for whacking a μOP based upon the criticality of that μOP. Also disclosed are embodiments of a method for determining the criticality of a μOP.


6
Aravindh Baktha, KS Venkatraman, Darrell D Boggs: Instruction packer for digital signal processor. Richard Calderwood, Stexar, April 12, 2007: US20070083736-A1

A digital signal processor which uses a RISC/CISC style front end and a VLIW style back end. Sequential ISA instructions are decoded into μops having a programmatic ordering. The μops are packed into a VLIW-like instruction packet according to a set of rules enforcing machine policy on e.g. data dep ...


7
Per Hammarlund, Aravindh Baktha, Michael D Upton, K S Venkatraman: Use of a context identifier in a cache memory. Blakely Sokoloff Taylor & Zafman, September 25, 2003: US20030182512-A1

A context identifier is used in a cache memory apparatus. The context identifier may be written into the tag of a cache line or may be written as an addition to the tag of a cache line, during cache write operation. During a cache read operation, the context identifier of as issued instruction may b ...


8
Aravindh Baktha, Michael D Upton, Thomas R Huff: Controlling a store data forwarding mechanism during execution of a load operation. Blakely Sokoloff Taylor & Zafman, September 18, 2003: US20030177312-A1

In an out-of-order execution computer system, a fast store forwarding buffer (FSFB) is conditionally signaled to output buffered store data of buffered memory store instructions to fill a buffered memory load instruction. The FSFB is coupled to a rotator so that the store data can be rotated from a ...


9
Harish Kumar, Aravindh Baktha, Mike D Upton, KS Venkatraman, Herbert H Hum, Zhongying Zhang: Method and apparatus for handling locks. Blakely Sokoloff Taylor & Zafman, November 6, 2003: US20030208647-A1

A method and device for determining an attribute associated with a locked load instruction and selecting a lock protocol based upon the attribute of the locked load instruction. Also disclosed is a method for concurrently executing the respective lock sequences associated with multiple threads of a ...


10
Per H Hammarlund, Stephan Jourdan, Sebastien Hily, Aravindh Baktha, Hermann Gartler: Apparatus and method for store address for store address prefetch and line locking. Intel Corporation, Kenyon & Kenyon, June 23, 2005: US20050138295-A1

Embodiments of the present invention relate to a memory management scheme and apparatus that enables efficient cache memory management. The method includes writing an entry to a store buffer at execute time; determining if the entry's address is in a first-level cache associated with the store buffe ...