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Or Bach Zvi, Avram Petrica, Iacobut Romeo, Apostol Adrian, Wurman Ze Ev, Leventhal Adam, Zeman Richard, Kapel Alon, Grigore George Catalin: Structured integrated circuit device. Easic Corporation, Or Bach Zvi, Avram Petrica, Iacobut Romeo, Apostol Adrian, Wurman Ze Ev, Leventhal Adam, Zeman Richard, Kapel Alon, Grigore George Catalin, GLUCK Jeffrey W, February 9, 2006: WO/2006/014849 (180 worldwide citation)

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM b ...


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Or Bach Zvi, Cooke Laurence, Apostol Adrian, Iacobut Romeo: Method for fabrication of semiconductor device. Easic, September 28, 2005: EP1579495-A2

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/O ...


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Or Bach Zvi, Avram Petrica, Iacobut Romeo, Apostol Adrian, Wurman Ze Ev, Leventhal Adam, Zeman Richard: Structured integrated circuit device. Easic, Kapel Alon, Grigore George Catalin, April 25, 2007: EP1776762-A2

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM b ...


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Kapel Alon, Grigore George Catalin, Or Bach Zvi, Avram Petrica, Iacobut Romeo, Apostol Adrian, Wurman Ze Ev, Leventhal Adam, Zeman Richard: Structured integrated circuit device. Easic, Kapel Alon, Grigore George Catalin, April 7, 2010: EP2173034-A2

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM b ...


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Or Bach Zvi, Cooke Laurence, Apostol Adrian, Iacobut Romeo: Method for fabrication of semiconductor device. Easic Corporation, GLUCK Jeffrey W Ph D, July 22, 2004: WO/2004/061903

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/O ...


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Or Bach Zvi, Cooke Laurence, Apostol Adrian, Iacobut Romeo: Method for fabrication of semiconductor device. Easic, chen ruifeng, March 8, 2006: CN200380109329

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/O ...


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Or Bach Zvi, Cooke Laurence, Apostol Adrian, Iacobut Romeo: Method for fabrication of semiconductor device. Easic Corporation, November 24, 2005: KR1020057011471

A novel method is presented to provide ASICs with drastically reduced NRE and with volume flexibility. The invention includes a method of fabricating an integrated circuit, including the steps of: providing a semiconductor substrate, forming a borderless logic array including a plurality of Area I/O ...


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Kapel Alon, Grigore George Catalin, Or Bach Zvi, Avram Petrica, Iacobut Romeo, Apostol Adrian, Wurman Zeev, Leventhal Adam, Zeman Richard: Structured integrated circuit device. Easic Corporation, August 28, 2007: KR1020077003697

A configurable logic array may include: a multiplicity of logic cells, containing look-up tables; customizable metal and via connection layers overlaying the multiplicity of logic cells; a multiplicity of device customizable I/O cells; a multiplicity of configuration customizable RAM blocks; a ROM b ...