1
Patrick R Bisson, Paul M Elliott, Kate B Amon, Anurag Nigam, Phu S Le: BLSR node extension. Cisco Systems, Tom Chen, Skjerven Morrill MacPherson, February 19, 2002: US06349092 (10 worldwide citation)

The present invention provides a method and structure for allowing more than 16 nodes to be configured in a single SONET BLSR network by utilizing unused portions of the transport overhead of an STS-N frame to expand the node identification field from 4 bits to 8 bits, thereby allowing up to 256 nod ...


2
Victor Shadan, Anurag Nigam: Dynamically controlled, cross-stacked CAM cell. Intel Corporation, Blakely Sokoloff Taylor & Zafman, December 30, 1997: US05703803 (8 worldwide citation)

A memory cell comprising a storage cell and a comparison circuit. The storage cell has a second node and a third node. The comparison circuit is coupled to the storage cell and comprises a first plurality of transistors coupled in series to a first input and a second plurality of transistors coupled ...


3
H Victor Shadan, Anurag Nigam: Mutually controlled match-line-to-word-line transfer circuit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, April 13, 1999: US05893929 (7 worldwide citation)

A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate ...


4
Nilay D Jani, Anurag Nigam, Cynthia M Furse: System and method for characterizing a signal path using a sub-chip sampler. University of Utah Research Foundation, Thorp North & Western, January 16, 2007: US07165200 (7 worldwide citation)

A system and method are disclosed for characterizing a signal path. The system includes a system clock configured to produce a system clock signal at a sample frequency. A frequency divider is configured to divide the sample frequency of the system clock signal by a factor of N to produce a chip clo ...


5
Anurag Nigam, David Stiles: Any size and location of concatenated packet data across SONET frames in a SONET signal. Redback Networks, Blakely Sokoloff Taylor & Zafman, January 31, 2006: US06993047 (6 worldwide citation)

Any size and location of concatenated packet data across Synchronous Optical Network (SONET) frames in a SONET signal is provided. In one embodiment, a method may include receiving portions of packets and placing the portions into buffers. Additionally, the method may determine packet boundaries amo ...


6
H Victor Shadan, Anurag Nigam: Mutually controlled match-line-to-word-line transfer circuit. Intel Corporation, Blakely Sokoloff Taylor & Zafman, January 4, 2000: US06012133 (2 worldwide citation)

A circuit for transferring a logic value from a content addressable memory (CAM) having a plurality of match lines to a random access memory (RAM) having a plurality of word lines. A first logic gate has an input coupled to a first match line of the plurality of match lines, and a second logic gate ...


7
Anurag Nigam, David Stiles: Any size and location of concatenated packet data across SONET frames in a SONET signal. Redback Networks, Blakely Sokoloff Taylor & Zafman, December 2, 2008: US07460554 (1 worldwide citation)

A method and apparatus for the incorporation of any size and location of concatenated SONET frames, which carry packet data, in an SONET signal are described. In an embodiment, a method includes receiving packet data. Additionally, the method includes concatenating the packet data into a Time Divisi ...


8
Yingchang Chen, Jeffrey Koonyee Lee, Chang Siau, Anurag Nigam, Thomas Yan: Word line compensation for memory arrays. SanDisk Technologies, Vierra Magen Marcus, March 14, 2017: US09595323 (1 worldwide citation)

A method is provided for operating a non-volatile storage system that includes a plurality of bit lines, a word line comb including a plurality of word lines, and a plurality of memory elements, each memory element coupled between one of the bit lines and one of the word lines. The method includes r ...


9
James Wang, Anurag Nigam, David R Stiles: Onboard RAM based FIFO with pointers to buffer overhead bytes of synchronous payload envelopes in synchronous optical networks. Redback Networks, Blakely Sokoloff Taylor & Zafman, October 2, 2007: US07277447 (1 worldwide citation)

An on-chip RAM FIFO (first-in-first-out) buffer for storing SPE overhead bytes wherein each entry of the RAM FIFO stores (1) a byte of the SPE overhead; (2) an indication of which byte of the SPE overhead is currently stored in that entry; and (3) an indication of which STS signal that byte was take ...


10
Anurag Nigam, Yingchang Chen: Leakage current compensation with reference bit line sensing in non-volatile memory. SanDisk Technologies, Vierra Magen Marcus, July 12, 2016: US09390793 (1 worldwide citation)

A non-volatile memory includes a sense amplifier that uses a reference bit line. The sense amplifier includes a first capacitor coupled to a selected bit line and a second capacitor coupled to a reference bit line. The reference capacitor compensates for displacement currents in the selected bit lin ...